peripherals_lpc23xx.h

Show hou use semaphores in RTL-ARM

/* 
 ********************************************************************
 * Project:    GNU-Port FreeRTOS Port
 * File:    	peripherals_lpc23xx.h
 *
 * System:   	ARM7TDMI-S 32 Bit (LPC2378)
 * Compiler:  	GCC 4.0.3
 *
 * Date:      	2006-11-17
 * Author:    	Grohmann
 *
 * Rights:    	Hitex Development Tools GmbH
 *            	Greschbachstr. 12
 *            	D-76229 Karlsruhe
 ********************************************************************
 * Description:
 *
 * This file is part of the GNU FreeRTOS Port
 * The code is based on the FreeRTOS originated by Richard Barry
 * This is a small implementation preemtive and semaphore task. 
 * The application runs in ARM mode with high optimization level.
 *	
 ********************************************************************
 * History:
 *
 *  Revision 1.0    2006/11/17      Gn
 *     Initial revision 
 ********************************************************************
 * This is a preliminary version.
 *
 * WARRANTY:  HITEX warrants that the media on which the SOFTWARE is 
 * furnished is free from defects in materials and workmanship under 
 * normal use and service for a period of ninety (90) days. HITEX entire
 * liability and your exclusive remedy shall be the replacement of the 
 * SOFTWARE if the media is defective. This Warranty is void if failure
 * of the media resulted from unauthorized modification, accident, abuse,
 * or misapplication.
 *
 * DISCLAIMER:  OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED
 * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES,
 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING
 * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR
 * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT
 * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY 
 * OF SUCH DAMAGES.
 ********************************************************************/


#ifndef _PERIPHERALS_LPC23XX_H_
#define _PERIPHERALS_LPC23XX_H_


/*
 *********************************************************************
 * PIN Connect Block 
 *********************************************************************
 */

#define PINSEL0        (*(REG32 0xE002C000))
#define PINSEL1        (*(REG32 0xE002C004))
#define PINSEL2        (*(REG32 0xE002C008))
#define PINSEL3        (*(REG32 0xE002C00C))
#define PINSEL4        (*(REG32 0xE002C010))
#define PINSEL5        (*(REG32 0xE002C014))
#define PINSEL6        (*(REG32 0xE002C018))
#define PINSEL7        (*(REG32 0xE002C01C))
#define PINSEL8        (*(REG32 0xE002C020))
#define PINSEL9        (*(REG32 0xE002C024))
#define PINSEL10       (*(REG32 0xE002C028))

// each PIN could have up to 4 software selectable functions
#define PINFUNC1		0x00
#define PINFUNC2		0x01
#define PINFUNC3		0x02
#define PINFUNC4		0x03


/*
 *********************************************************************
 * Power Control 
 *********************************************************************
 */
 
#define PCON           	(*(REG32 0xE01FC0C0))	// power control
#define PCONP          	(*(REG32 0xE01FC0C4))	// interrupt wake
#define INTWAKE			    (*(REG32 0xE01FC144))	// power control for peripherals

/* Bit masks for Interrupt wake register */
#define INTW_EXT0		(0x00000001	<< 0)
#define INTW_EXT1		(0x00000001 << 1)
#define INTW_EXT2		(0x00000001 << 2)
#define INTW_EXT3		(0x00000001 << 3)
#define INTW_ETH		(0x00000001 << 4)
#define INTW_USB		(0x00000001	<< 5)
#define INTW_CAN		(0x00000001 << 6)
#define INTW_GPIO		(0x00000001 << 7)
#define INTW_BOD		(0x00000001 << 14)
#define INTW_RTC		(0x00000001 << 15)



/* peripheral Bit masks for peripherals power control */
#define PCON_TIM0		0x00000001
#define PCON_TIM1		0x00000002
#define PCON_UART0		0x00000004
#define PCON_UART1		0x00000008
#define PCON_ENET		0x40000000

/*!
 *********************************************************************
 * Vectored Interrupt Controller (VIC) 
 *********************************************************************
 */

#define		VIC_Base	0xFFFFF000;


#define VICIRQStatus   		(*(REG32 0xFFFFF000))
#define VICFIQStatus   		(*(REG32 0xFFFFF004))
#define VICRawIntr     		(*(REG32 0xFFFFF008))
#define VICIntSelect   		(*(REG32 0xFFFFF00C))
#define VICIntEnable   		(*(REG32 0xFFFFF010))
#define VICIntEnClr    		(*(REG32 0xFFFFF014))
#define VICSoftInt     		(*(REG32 0xFFFFF018))
#define VICSoftIntClr  		(*(REG32 0xFFFFF01C))
#define VICProtection  		(*(REG32 0xFFFFF020))
#define VICSWPriorityMask  	(*(REG32 0xFFFFF024))

#define VICVectAddr    (*(REG32  0xFFFFFF00))

#define VICVectAddr0   (*(REG32  0xFFFFF100))
#define VICVectAddr1   (*(REG32  0xFFFFF104))
#define VICVectAddr2   (*(REG32  0xFFFFF108))
#define VICVectAddr3   (*(REG32  0xFFFFF10C))
#define VICVectAddr4   (*(REG32  0xFFFFF110))
#define VICVectAddr5   (*(REG32  0xFFFFF114))
#define VICVectAddr6   (*(REG32  0xFFFFF118))
#define VICVectAddr7   (*(REG32  0xFFFFF11C))
#define VICVectAddr8   (*(REG32  0xFFFFF120))
#define VICVectAddr9   (*(REG32  0xFFFFF124))
#define VICVectAddr10  (*(REG32  0xFFFFF128))
#define VICVectAddr11  (*(REG32  0xFFFFF12C))
#define VICVectAddr12  (*(REG32  0xFFFFF130))
#define VICVectAddr13  (*(REG32  0xFFFFF134))
#define VICVectAddr14  (*(REG32  0xFFFFF138))
#define VICVectAddr15  (*(REG32  0xFFFFF13C))
#define VICVectAddr16  (*(REG32  0xFFFFF140))
#define VICVectAddr17  (*(REG32  0xFFFFF144))
#define VICVectAddr18  (*(REG32  0xFFFFF148))
#define VICVectAddr19  (*(REG32  0xFFFFF14C))
#define VICVectAddr20  (*(REG32  0xFFFFF150))
#define VICVectAddr21  (*(REG32  0xFFFFF154))
#define VICVectAddr22  (*(REG32  0xFFFFF158))
#define VICVectAddr23  (*(REG32  0xFFFFF15C))
#define VICVectAddr24  (*(REG32  0xFFFFF160))
#define VICVectAddr25  (*(REG32  0xFFFFF164))
#define VICVectAddr26  (*(REG32  0xFFFFF168))
#define VICVectAddr27  (*(REG32  0xFFFFF16C))
#define VICVectAddr28  (*(REG32  0xFFFFF170))
#define VICVectAddr29  (*(REG32  0xFFFFF174))
#define VICVectAddr30  (*(REG32  0xFFFFF178))
#define VICVectAddr31  (*(REG32  0xFFFFF17C))

#define VICVectPriority0   (*(REG32 0xFFFFF200) )
#define VICVectPriority1   (*(REG32 0xFFFFF204))
#define VICVectPriority2   (*(REG32 0xFFFFF208))
#define VICVectPriority3   (*(REG32 0xFFFFF20C))
#define VICVectPriority4   (*(REG32 0xFFFFF210))
#define VICVectPriority5   (*(REG32 0xFFFFF214))
#define VICVectPriority6   (*(REG32 0xFFFFF218))
#define VICVectPriority7   (*(REG32 0xFFFFF21C))
#define VICVectPriority8   (*(REG32 0xFFFFF220))
#define VICVectPriority9   (*(REG32 0xFFFFF224))
#define VICVectPriority10  (*(REG32 0xFFFFF228))
#define VICVectPriority11  (*(REG32 0xFFFFF22C))
#define VICVectPriority12  (*(REG32 0xFFFFF230))
#define VICVectPriority13  (*(REG32 0xFFFFF234))
#define VICVectPriority14  (*(REG32 0xFFFFF238))
#define VICVectPriority15  (*(REG32 0xFFFFF23C))
#define VICVectPriority16  (*(REG32 0xFFFFF240))
#define VICVectPriority17  (*(REG32 0xFFFFF244))
#define VICVectPriority18  (*(REG32 0xFFFFF248))
#define VICVectPriority19  (*(REG32 0xFFFFF24C))
#define VICVectPriority20  (*(REG32 0xFFFFF250))
#define VICVectPriority21  (*(REG32 0xFFFFF254))
#define VICVectPriority22  (*(REG32 0xFFFFF258))
#define VICVectPriority23  (*(REG32 0xFFFFF25C))
#define VICVectPriority24  (*(REG32 0xFFFFF260))
#define VICVectPriority25  (*(REG32 0xFFFFF264))
#define VICVectPriority26  (*(REG32 0xFFFFF268))
#define VICVectPriority27  (*(REG32 0xFFFFF26C))
#define VICVectPriority28  (*(REG32 0xFFFFF270))
#define VICVectPriority29  (*(REG32 0xFFFFF274))
#define VICVectPriority30  (*(REG32 0xFFFFF278))
#define VICVectPriority31  (*(REG32 0xFFFFF27C))
                           
#define VIC_VectAdr		(*(REG32 (0xFFFFFF00) ))	// current VectorAdr

/*##############################################################################
## Peripheral Clock selsction
##############################################################################*/
#define PCLKSEL0      (*(REG32 (0xE01FC1A8) ))
#define PCLKSEL1      (*(REG32 (0xE01FC1AC) ))
#define PCLK_GPIO_1   (0x00000004)
#define PCLK_GPIO_2   (0x00000008)
#define PCLK_GPIO_4   (0x00000000)



/*##############################################################################
## Ethernet Controller
##############################################################################*/

// MAC registers

#define ETH_MAC1		(*(REG32 0xFFE00000))
#define ETH_MAC2		(*(REG32 0xFFE00004))
#define ETH_IPGT		(*(REG32 0xFFE00008))
#define ETH_IPGR		(*(REG32 0xFFE0000C))
#define ETH_CLRT		(*(REG32 0xFFE00010))
#define ETH_MAXF		(*(REG32 0xFFE00014))
#define ETH_PHYSUPP		(*(REG32 0xFFE00018))
#define ETH_TEST		(*(REG32 0xFFE0001C))

// MII management & config registers
#define ETH_MIICFG		(*(REG32 0xFFE00020))
#define ETH_MIICMD		(*(REG32 0xFFE00024))
#define ETH_MIIADR		(*(REG32 0xFFE00028))
#define ETH_MIIWTD		(*(REG32 0xFFE0002C))
#define ETH_MIIRDD		(*(REG32 0xFFE00030))
#define ETH_MIIIND		(*(REG32 0xFFE00034))


#define ETH_SA0			(*(REG32 0xFFE00040))
#define ETH_SA1			(*(REG32 0xFFE00044))
#define ETH_SA2			(*(REG32 0xFFE00048))

// Control Register

#define ETH_COMMAND		(*(REG32 0xFFE00100))
#define ETH_STATUS		(*(REG32 0xFFE00104))

#define ETH_RXDESC		(*(REG32 0xFFE00108))
#define ETH_RXSTAT		(*(REG32 0xFFE0010C))
#define ETH_RXDESCRNO	(*(REG32 0xFFE00110))
#define ETH_RXPRODIX	(*(REG32 0xFFE00114))
#define ETH_RXCONSIX	(*(REG32 0xFFE00118))

#define ETH_TXDESC		(*(REG32 0xFFE0011C))
#define ETH_TXSTAT		(*(REG32 0xFFE00120))
#define ETH_TXDESCRNO	(*(REG32 0xFFE00124))
#define ETH_TXPRODIX	(*(REG32 0xFFE00128))
#define ETH_TXCONSIX	(*(REG32 0xFFE0012C))

#define ETH_TSV0		(*(REG32 0xFFE00158))