📄 startup.s
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/*
********************************************************************
* Project:
* File: startup.s
* System:
* Compiler: GCC 4.0.0
* Date: 2006-08-22
* Author: Wenz
* Rights: Hitex Development Tools GmbH
* Greschbachstr. 12
* D-76229 Karlsruhe
*
********************************************************************
* Description
* - boot code for ARM7 based LPC23xx controller
*
*
********************************************************************
*
* History:
*
* Initial revision
*
*
********************************************************************
*/
.extern main
.extern tc0_interrupt
.global _app_entry
.global _startup
.global _tc0_srv
.global _enableInterrupts
.global IRQ_Handler
# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
# Stack size definitions
.equ USR_Stack_Size, 0x4
.equ FIQ_Stack_Size, 0x4
.equ IRQ_Stack_Size, 0x200
.equ SVC_Stack_Size, 0x400
.equ ABT_Stack_Size, 0x4
.equ UND_Stack_Size, 0x4
# configure startup code according your needs
.equ PLL_SETUP, 1
.equ MAM_SETUP, 1
.equ APB_SETUP, 1
#
# register definitions
#
# system control block
.equ SCB_BASE, 0xE01FC000
.equ SCBOFF_EXTINT, 0x140
.equ SCBOFF_EXTMODE, 0x148
.equ SCBOFF_EXTPOLAR, 0x14C
.equ SCBOFF_RSID, 0x180
.equ SCBOFF_CSPR, 0x184
.equ SCBOFF_AHBCFG1, 0x188
.equ SCBOFF_AHBCFG2, 0x18C
.equ SCBOFF_SCS, 0x1A0
.equ SCBOFF_CLKSRCSEL, 0x10C
.equ SCBOFF_PLLCON, 0x080
.equ SCBOFF_PLLCFG, 0x084
.equ SCBOFF_PLLSTAT, 0x088
.equ SCBOFF_PLLFEED, 0x08C
.equ SCBOFF_CCLKCFG, 0x104
.equ SCBOFF_USBCLKCFG, 0x108
.equ SCBOFF_APBDIV, 0x100
.equ SCBOFF_PCLKSEL0, 0x1A8
.equ SCBOFF_PCLKSEL1, 0x1AC
.equ SCBOFF_PCON, 0x0C0
.equ SCBOFF_INTWAKE, 0x144
.equ SCBOFF_PCONP, 0x0C4
# Peripheral clock divider
.equ APBDIV, 0xE01FC100
# Memory Accelerator Module (MAM) definitions
.equ MAM_BASE, 0xE01FC000 /* MAM Base Address */
.equ MAMCR_OFS, 0x00 /* MAM Control Offset */
.equ MAMTIM_OFS, 0x04 /* MAM Timing Offset */
# Startup Code must be linked first at Address at which it expects to run.
.section .start, "ax"
.code 32
.align 0
_startup:
ENTRY:
# Exception Vectors
Vectors:
LDR PC, Reset_Addr /* 0x0000 */
LDR PC, Undef_Addr /* 0x0004 */
LDR PC, SWI_Addr /* 0x0008 */
LDR PC, PAbt_Addr /* 0x000C */
LDR PC, DAbt_Addr /* 0x0010 */
.word 0xB9206E50 /* 0x0014 Reserved Vector */
LDR PC, [PC, #-0x120] /* 0x0018 Vector from VIC */
LDR PC, FIQ_Addr /* 0x001C FIQ has no vector! */
Reset_Addr: .word Hard_Reset
Undef_Addr: .word Undef_Handler
SWI_Addr: .word SWI_Handler
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
.word 0 /* Reserved Address */
IRQ_Addr: .word IRQ_Handler
FIQ_Addr: .word FIQ_Handler
Undef_Handler: B Undef_Handler
SWI_Handler: B SWI_Handler
PAbt_Handler: B PAbt_Handler
DAbt_Handler: B DAbt_Handler
IRQ_Handler: B IRQ_Handler /* should never get here ... */
FIQ_Handler: B FIQ_Handler
.text
.arm
.align 0
DelayMax: .word 0x8000
# Reset Handler
.func _startup
Hard_Reset:
_app_entry:
# Delay for emulator
ldr r1, DelayMax
mov r0, #0
DelayLoop:
cmp r0, r1
add r0, r0, #1
blo DelayLoop
# Setup APDDIV
.ifdef APB_SETUP
ldr R0, =APBDIV
ldr R1, =0x00
str R1, [R0]
.endif
# Setup Clock and PLL
.ifdef PLL_SETUP
.equ SCS_Val, 0x00000020
.equ CLKSRCSEL_Val, 0x00000001
.equ PLLCFG_Val, 0x0000000D
.equ CCLKCFG_Val, 0x00000006
.equ USBCLKCFG_Val, 0x00000000
.equ PCLKSEL0_Val, 0x00000000
.equ PCLKSEL1_Val, 0x00000000
.equ PLLSTAT_M, 0x00007FFF /* PLL M Value */
.equ PLLSTAT_N, 0x00FF0000 /* PLL N Value */
.equ PLLSTAT_PLOCK, 0x04000000 /* PLL Lock Status */
ldr r0, =SCB_BASE
mov r1, #0xAA
mov r2, #0x55
# Configure and Enable PLL
ldr r3, =SCS_Val /* Enable main oscillator */
str r3, [r0, #SCBOFF_SCS]
ldr r4, =SCS_Val
OSC:
ldr r3, [r0, #SCBOFF_SCS] /* Wait for main osc stabilize */
and r3, r3, r4
cmp r3, r4
bne OSC
ldr r3, =CLKSRCSEL_Val /* Select PLL source clock */
str r3, [r0, #SCBOFF_CLKSRCSEL]
ldr r3, =PLLCFG_Val /* PLL Config */
str r3, [r0, #SCBOFF_PLLCFG]
str r1, [r0, #SCBOFF_PLLFEED]
str r2, [r0, #SCBOFF_PLLFEED]
mov r3, #0x01 /* enable PLL */
str r3, [r0, #SCBOFF_PLLCON]
str r1, [r0, #SCBOFF_PLLFEED]
str r2, [r0, #SCBOFF_PLLFEED]
# Wait until PLL Locked
ldr r4, =PLLSTAT_PLOCK
LoopPLL:
ldr R3, [r0, #SCBOFF_PLLSTAT]
and r3, r3, r4
cmp r3, r4
bne LoopPLL
MN_Lock:
ldr r3, [r0, #SCBOFF_PLLSTAT]
ldr r4, =(PLLSTAT_M | PLLSTAT_N)
and r3, r3, r4
ldr r4, =PLLCFG_Val /* PLL Config value */
eors r3, r3, r4
bne MN_Lock
# Setup CPU clock divider
# main clock is 12Mhz now divided by 6
mov r3, #CCLKCFG_Val /* clock config value */
str r3, [r0, #SCBOFF_CCLKCFG]
# Setup Peripheral Clock
mov r3, #PCLKSEL0_Val /* clock selector value 0 */
str r3, [r0, #SCBOFF_PCLKSEL0]
ldr r3, =PCLKSEL1_Val /* clock selector value 1 */
str r3, [r0, #SCBOFF_PCLKSEL1]
# Switch to PLL Clock
# PLL clock is 2 x 12 x 12 / 6 --> 48 MHz
mov r3, #0x03 /* PLL enable & connect */
str r3, [r0, #SCBOFF_PLLCON]
str r1, [r0, #SCBOFF_PLLFEED]
str r2, [r0, #SCBOFF_PLLFEED]
.endif
# setup memory accelerator
.ifdef MAM_SETUP
.equ MAMCR_Val, 0x00000002
.equ MAMTIM_Val, 0x00000004
ldr r0, =MAM_BASE
mov r1, #MAMTIM_Val
str r1, [r0, #MAMTIM_OFS]
mov r1, #MAMCR_Val
str r1, [r0, #MAMCR_OFS]
.endif
# Setup Stack for each mode
ldr r0, =_top_stack_
# Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #Mode_FIQ|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #FIQ_Stack_Size
# Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #Mode_IRQ|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #IRQ_Stack_Size
# Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #Mode_ABT|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #ABT_Stack_Size
# Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #Mode_UND|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #UND_Stack_Size
# Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #Mode_SVC|I_BIT|F_BIT
mov r13, r0
# Setup a default Stack Limit (when compiled with "-mapcs-stack-check")
sub SL, SP, #1<<10 /* 1kB */
# Relocate .data section (Copy from ROM to RAM)
LDR R1, =_etext
LDR R2, =_data
LDR R3, =_edata
LoopRel:
CMP R2, R3
LDRLO R0, [R1], #4
STRLO R0, [R2], #4
BLO LoopRel
# Clear .bss section (Zero init)
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
LoopZI:
CMP R1, R2
STRLO R0, [R1], #4
BLO LoopZI
# Enter the C code
B main
endless_loop:
B endless_loop
.endfunc
###################################################
#
# enable IRQ and FIQ at core
#
###################################################
.func _enableInterrupts
_enableInterrupts:
stmfd sp!, {r1}
mrs r1, CPSR
bic r1, r1, #I_BIT
bic r1, r1, #F_BIT
msr CPSR_c, r1
ldmfd sp!, {r1}
mov pc, r14
.size __enableInterrupts, . - __enableInterrupts
.endfunc
###################################################
#
# primary interrupt service for tc0 compare interrupt
#
###################################################
.end
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