start.asm

FreeRTOS is a portable, open source, mini Real Time Kernel - a free to download and royalty free RTO

#set      BDM_PFCS0       0x0000   ; <<< set default breakpoint
#set      BDM_PFCS1       0x0000   ; configurations 
#set      BDM_PFCS2       0x0000
#set      BDM_PFCS3       0x0000

#set      BDM_PFA0        0xFFFFFF ; <<< set address
#set      BDM_PFA1        0xFFFFFF ; configurations
#set      BDM_PFA2        0xFFFFFF
#set      BDM_PFA3        0xFFFFFF
#set      BDM_PFA4        0xFFFFFF
#set      BDM_PFA5        0xFFFFFF
#set      BDM_PFA6        0xFFFFFF
#set      BDM_PFA7        0xFFFFFF

#set      BDM_PFD0        0xFFFFFF ; <<< set patch data 
#set      BDM_PFD1        0xFFFFFF ; configurations
#set      BDM_PFD2        0xFFFFFF
#set      BDM_PFD3        0xFFFFFF
#set      BDM_PFD4        0xFFFFFF
#set      BDM_PFD5        0xFFFFFF
#set      BDM_PFD6        0xFFFFFF
#set      BDM_PFD7        0xFFFFFF


; <<< END OF SETTINGS >>>

;====================================================================
; 5  Section and Data Declaration
;====================================================================

;====================================================================
; 5.1  Several fixed addresses (fixed for MB963xx controllers)
;====================================================================

MFMCS      .EQU      0x03F1          ; Main Flash Memory configuration register
MFMTC      .EQU      0x03F2          ; Main Flash Memory timing register
SFMCS      .EQU      0x03F5          ; Satellite Flash Memory configuration register
SFMTC      .EQU      0x03F6          ; Satellite Flash Memory timing register
ROMM       .EQU      0x03AE          ; ROM mirror control register
CKSR       .EQU      0x0401          ; Clock select control register
CKSSR      .EQU      0x0402          ; Clock stabilization select register
CKMR       .EQU      0x0403          ; Clock monitor register
CKFCR      .EQU      0x0404          ; Clock frequency control register
PLLCR      .EQU      0x0406          ; PLL control register
VRCR       .EQU      0x042C          ; Voltage Regulator Control register
#if BUSMODE != SINGLE_CHIP           ; only for devices with external bus
PIER00     .EQU      0x0444
PIER01     .EQU      0x0445
PIER02     .EQU      0x0446
PIER03     .EQU      0x0447
PIER12     .EQU      0x0450
EACL0      .EQU      0x06E0
EACH0      .EQU      0x06E1
EACL1      .EQU      0x06E2
EACH1      .EQU      0x06E3
EACL2      .EQU      0x06E4
EACH2      .EQU      0x06E5
EACL3      .EQU      0x06E6
EACH3      .EQU      0x06E7
EACL4      .EQU      0x06E8
EACH4      .EQU      0x06E9
EACL5      .EQU      0x06EA
EACH5      .EQU      0x06EB
EAS2       .EQU      0x06EC
EAS3       .EQU      0x06ED
EAS4       .EQU      0x06EE
EAS5       .EQU      0x06EF
EBM        .EQU      0x06F0
EBCF       .EQU      0x06F1
EBAE0      .EQU      0x06F2
EBAE1      .EQU      0x06F3
EBAE2      .EQU      0x06F4
EBCS       .EQU      0x06F5
#endif ; BUSMODE != SINGLE_CHIP

;====================================================================
; 5.2  Declaration of __near addressed data sections
;====================================================================

; sections to be cleared
          .SECTION  DATA,      DATA,   ALIGN=2  ; zero clear area
          .SECTION  DATA2,     DATA,   ALIGN=2  ; zero clear area
          .SECTION  DIRDATA,   DIR,    ALIGN=2  ; zero clear direct
          .SECTION  LIBDATA,   DATA,   ALIGN=2  ; zero clear lib area

; sections to be initialised with start-up values
          .SECTION  INIT,      DATA,   ALIGN=2  ; initialised area
          .SECTION  INIT2,     DATA,   ALIGN=2  ; initialised area
          .SECTION  DIRINIT,   DIR,    ALIGN=2  ; initialised dir
          .SECTION  LIBINIT,   DATA,   ALIGN=2  ; initialised lib area
#if CONSTDATA == RAMCONST
          .SECTION  CINIT,     DATA,   ALIGN=2  ; initialised const
          .SECTION  CINIT2,    DATA,   ALIGN=2  ; initialised const
#endif

; sections containing start-up values for initialised sections above
          .SECTION  DCONST,    CONST,  ALIGN=2  ; DINIT initialisers
          .SECTION  DIRCONST, DIRCONST,ALIGN=2  ; DIRINIT initialisers
          .SECTION  LIBDCONST, CONST,  ALIGN=2  ; LIBDCONST init val

          ; following section is either copied to CINIT (RAMCONST) or
          ; mapped by ROM-mirror function (ROMCONST)
          .SECTION  CONST,     CONST,  ALIGN=2  ; CINIT initialisers
          .SECTION  CONST2,    CONST,  ALIGN=2  ; CINIT initialisers

;====================================================================
; 5.3  Declaration of RAMCODE section and labels
;====================================================================

#if COPY_RAMCODE == ON
          .SECTION  RAMCODE,   CODE,  ALIGN=1  
          .IMPORT _RAM_RAMCODE                  ; provided by linker
          .IMPORT _ROM_RAMCODE                  ; provided by linker
#endif


;====================================================================
; 5.4  Declaration of sections containing other sections description
;====================================================================

; DCLEAR contains start address and size of all sections to be cleared
; DTRANS contains source and destination address and size of all 
; sections to be initialised with start-up values
; The compiler automatically adds a descriptor for each __far addressed
; data section to DCLEAR or DTRANS. These __far sections are separated 
; for each C-module.

; In addition the start-up file adds the descriptors of the previously
; declared __near section here. This way the same code in the start-up
; file can be used for initialising all sections.

   .SECTION  DCLEAR,    CONST,  ALIGN=2  ; zero clear table
   ;    Address         Bank            Size
   .DATA.H DATA,    BNKSEC DATA,    SIZEOF(DATA   )
   .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA)
   .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA)

   .SECTION  DTRANS,    CONST,  ALIGN=2  ; copy table
   ;    Address         Bank               Address     Bank          Size
   .DATA.H DCONST,   BNKSEC DCONST,   INIT,   BNKSEC INIT,   SIZEOF INIT   
   .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT
   .DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT

#if CONSTDATA == RAMCONST
   .DATA.H CONST,    BNKSEC CONST,    CINIT,  BNKSEC CINIT,  SIZEOF CINIT  
   .DATA.H CONST2,   BNKSEC CONST,    CINIT2, BNKSEC CINIT2, SIZEOF CINIT2
#endif

#if COPY_RAMCODE == ON
   .DATA.L _ROM_RAMCODE, _RAM_RAMCODE
   .DATA.H SIZEOF RAMCODE
#endif

;====================================================================
; 5.5  Stack area and stack top definition/declaration
;====================================================================
#if STACK_RESERVE == ON
            .SECTION  SSTACK, STACK, ALIGN=2

            .EXPORT __systemstack, __systemstack_top
__systemstack:
            .RES.B    (STACK_SYS_SIZE + 1) & 0xFFFE
__systemstack_top:
SSTACK_TOP:

            .SECTION  USTACK, STACK, ALIGN=2

            .EXPORT __userstack, __userstack_top
__userstack:
            .RES.B    (STACK_USR_SIZE + 1) & 0xFFFE
__userstack_top:
USTACK_TOP:

#else
            .SECTION  SSTACK, STACK, ALIGN=2
            .SECTION  USTACK, STACK, ALIGN=2

            .IMPORT __systemstack, __systemstack_top
            .IMPORT __userstack, __userstack_top
#endif

;====================================================================
; 5.6  Direct page register dummy label definition
;====================================================================

          .SECTION  DIRDATA  ; zero clear direct
DIRDATA_S:                                      ; label for DPR init       

; This label is used to get the page of the __direct data.
; Depending on the linkage order of this startup file the label is
; placed anywhere within the __direct data page. However, the
; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower 
; 8 Bit of the address of DIRDATA_S are not relevant and this feature 
; becomes linkage order independent. 
; Note, the linker settings have to make sure that all __direct
; data are located within the same physical page (256 Byte block).

;====================================================================
; 6  Start-Up Code
;====================================================================

;====================================================================
; 6.1  Import external symbols
;====================================================================

          .IMPORT   _main                    ; user code entrance
#if CLIBINIT == ON
          .IMPORT   __stream_init
          .IMPORT   _exit
          .EXPORT   __exit
#endif          
          .EXPORT   _start

;====================================================================
;   ___  _____   __    ___  _____
;  /       |    /  \  |   \   |                  
;  \___    |   |    | |___/   |   
;      \   |   |----| |  \    |   
;   ___/   |   |    | |   \   |      Begin of actual code section
;====================================================================
          .SECTION  CODE_START, CODE, ALIGN=1

;====================================================================
; 6.2  Program start (the reset vector should point here)
;====================================================================
_start:
          NOP  ; This NOP is only for debugging. On debugger the IP
               ; (instruction pointer) should point here after reset

;====================================================================
; 6.3  "NOT RESET YET" WARNING
;====================================================================
notresetyet:
          NOP  ; read hint below!!!!!!!
; If the debugger stays at this NOP after download, the controller has
; not been reset yet. In order to reset all hardware registers it is
; highly recommended to reset the controller.
; However, if no reset vector has been defined on purpose, this start
; address can also be used.
; This mechanism is using the .END instruction at the end of this mo-
; dule. It is not necessary for controller operation but improves 
; security during debugging (mainly emulator debugger).
; If the debugger stays here after a single step from label "_start"
; to label "notresetyet", this note can be ignored.

;====================================================================
; 6.4  Initialisation of processor status
;====================================================================
          AND  CCR, #0x80          ; disable interrupts
          MOV  ILM,#7              ; set interrupt level mask to ALL
          MOV  RP,#REGBANK         ; set register bank pointer 

;====================================================================
; 6.5  Set clock ratio (ignore subclock)
;====================================================================
          MOVN A, #0               ; set bank 0 in DTB for the case that
          MOV  DTB, A              ; start-up code was not jumped by reset
		  
          MOV  CKSSR, #(0xF8 | MC_STAB_TIME)  ; set clock stabilization time

#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
          MOV  CKSR,  #0xB5
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)

#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
          CLRB MFMCS:4
          CLRB MFMCS:5
          CLRB SFMCS:4
          CLRB SFMCS:5
          MOVW CKFCR, #0x1111
          MOV  CKSR,  #0xB5
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)

#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
#  if ((SERIES == MB96340) && (DEVICE < 3))
          MOVW PLLCR, #0x00E0
          MOV  CKSR,  #0xFA
#  else
          MOVW PLLCR, #0x00A1
          MOVW CKFCR, #0x1111
          MOVW MFMTC, #0x2128
#    if SATELLITE_FLASH == ON
          MOVW SFMTC, #0x2128
#    endif ; SATELLITE_FLASH == ON
          MOV  CKSR,  #0xFA
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)