📄 start91460.asm
字号:
; ||||||____ BAAX / P10_2
; |||||_____ WEX / P10_3
; ||||______ MCLKO or !MCLKO / P10_4
; |||_______ MCLKI or !MCLKI/ P10_5
; ||________ MCLKE / P10_6
; |_________ -
;
#set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10
; ||||||||
; ||||||||__ 0:SYSCLK / 1:!SYSCLK
; |||||||___ -
; ||||||____ -
; |||||_____ -
; ||||______ 0:MCLKO / 1:!MCLKO
; |||_______ 0:MCLKI / 1:!MCLKI
; ||________ 0:MCLKI / 1:!MCLKI
; |_________ -
;
;
; Select if the ports are set to
; 1 : External bus mode, I/O for control lines or
; 0 : General I/O port (GIO)
;
; Note: Not all control-lines are supported by the different devices. Please check the
; data sheet.
;
;=========================================================================================
; 5 Definition of Configurations
;=========================================================================================
;
#set NOCLOCK 0 ; do not touch CKSCR register
#set MAINCLOCK 1 ; select main clock
; ; MB91461R : 1/4 of oscillation input
; ; Others: 1/2 of oscillation input
#set MAINPLLCLOCK 2 ; select main clock with PLL
#set SUBCLOCK 3 ; select subclock (if available)
;
#set PSCLOCK_CLKB 0x00 ; select core clock (initial)
#set PSCLOCK_PLL 0x10 ; select PLL output (x)
#set PSCLOCK_MAIN 0x30 ; select Main Oscillation
;
;=========================================================================================
; 5.1 CLOCKSPEED == CLOCK_USER <<<
;=========================================================================================
; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the
; corresponding application note.
;
#if (CLOCKSPEED == CLOCK_USER )
#set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource
#set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF
#set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
#set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG;
#set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz
#set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz
#set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz
#set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz
#set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD;
; Voltage Regulator
#set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;
#set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;
#set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;
#set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.2 CLOCKSPEED == NO_CLOCK
;=========================================================================================
;
#if (CLOCKSPEED == NO_CLOCK )
#set CLOCKSOURCE NOCLOCK
#endif
;
;=========================================================================================
; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ
;=========================================================================================
;
#if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91463N) || (DEVICE == MB91461R)
#error: Frequency is not supported by this device.
#endif
; End restriction
;
#set CLOCKSOURCE SUBCLOCK ; Clocksource
#set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF
#set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
#set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
#set MUL_G 0x0F ; 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz
#set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz
#set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz
#set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
#set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
; Voltage Regulator
#set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
#set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
#set FLASHREADT 0xC100 ; 0x7004h: FMWT;
#set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ
;=========================================================================================
;
#if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91461R)
#error: Frequency is not supported by this device.
#endif
; End restriction
;
#set CLOCKSOURCE MAINCLOCK ; Clocksource
#set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
#set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
#set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
#set MUL_G 0x0F ; 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz
#set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz
#set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz
#set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
#set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
; Voltage Regulator
#set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
#set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
#set FLASHREADT 0xC100 ; 0x7004h: FMWT;
#set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ
;=========================================================================================
;
#if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91461R)
#error: Frequency is not supported by this device.
#endif
; End restriction
;
#set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
#set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
#set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz
#set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
#set MUL_G 0x0B ; 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz
#set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz
#set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz
#set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz
#set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
; Voltage Regulator
#if (DEVICE == MB91469G)
#set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
#else
#set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
#endif
#set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
#set FLASHREADT 0xC201 ; 0x7004h: FMWT;
#set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
;=========================================================================================
;
#if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91461R)
#error: Frequency is not supported by this device.
#endif
; End restriction
;
#set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
#set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
#set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
#set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
#set MUL_G 0x0F ; 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
#set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
#set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
#set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
#set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
; Voltage Regulator
#set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
#set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
#set FLASHREADT 0xC413 ; 0x7004h: FMWT;
#set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ
;=========================================================================================
;
#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91461R)
#error: Frequency is not supported by this device.
#endif
; End restriction
;
#set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
#set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
#set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
#set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
#set MUL_G 0x13 ; 0x48Fh: PLLMULG;
; Clock Divider
#set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
#set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
#set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz
; CAN Clock
#set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
#set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
#set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
; Voltage Regulator
#set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
#set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
; Memory Controller
#set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
#set FLASHREADT 0xC413 ; 0x7004h: FMWT;
#set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
#endif
;
;=========================================================================================
; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ
;=========================================================================================
;
#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )
;
; Start restriction; Maximum frequency
#if (DEVICE == MB91461R)
#error: Frequency is not supported by this⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -