start91460.asm

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; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
;
;=========================================================================================
; 4.5  Low-Level Library Interface
;=========================================================================================
;
#set    CLIBINIT        OFF                     ; <<< select ext. libray usage
;
; This option has only to be set,  if  stream-IO/standard-IO function  of the C-libraray 
; have to be used (printf(), fopen()...).  This also requires  low-level functions to be 
; defined by the application software.
; For other library functions like (e.g. sprintf()) all this is not necessary.  However, 
; several functions consume a large amount of stack.
;
;=========================================================================================
; 4.6  C++ start-up 
;=========================================================================================
;
#set    CPLUSPLUS       OFF                     ; <<< activate if c++ files are used
;
; In the  C++ specifications,  when external  or static objects are used,  a constructor 
; must be called followed by  the main function.  Because four-byte pointers to the main 
; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from
; the  lower  address  of  the four  addresses  in that  section.  If using C++ sources, 
; activate this function to create the section EXT_CTOR_DTOR. 
;
;=========================================================================================
; 4.7  Clock Configuration
;=========================================================================================
;=========================================================================================
; 4.7.1  Clock Selection
;=========================================================================================
;
; No clock settings
#set    NO_CLOCK                                               0x01
;
; Sub-oscillation input: 32 kHz 
#set    SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ     0x11
;
; Oscillation input: 4 MHz 
#set    MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ     0x21
#set    PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ     0x22
#set    PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ     0x23
#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ     0x24
#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ     0x25
#set    PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ     0x26  ;not MB91V460, ...
#set    PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ     0x27  ;not MB91V460, ...
;
; MB91461R only: Oscillation input: 10 MHz
#set    PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x41
;
; MB91461R only: Oscillation input: 20 MHz
#set    PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x51
;
; User settings
#set    CLOCK_USER                                             0x61
;
;
;
#set    CLOCKSPEED      PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
;                                               ; <<< Select clock configuration 
;
; There are different default configurations available, where all necessary settings for 
; clocks and the related  registers are made.  Beside this configurations,  there is the
; possibility   to  define  a  user   configuration   in  the  chapter   "Definition  of 
; Configurations"
; 
; - NO_CLOCK means: 
;   The clock registers are not set by the start-up file.
;
; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:
;   Main oszillation        =  4 MHz, PLL is activated
;   CPU clock (CLKB)        = 64 MHZ
;   Peripheral clock (CLKP) = 16 MHZ
;   Ext. bus clock (CLKT)   = 32 MHZ
;   CAN clock (CLKCAN)      = 16 MHz, using PLLx 
;
; - CLOCK_USER: 
;   The user configuration definded in the chapter "Definition of Configurations" is set.
;
; Note: Not all  frequencies  are supported  by every device.  Please see  the  hardware 
;       manual.
;
;=========================================================================================
; 4.7.2  Select Clock Modulator  
;=========================================================================================
;
#set    CLOMO           OFF                     ; <<< Enable /disable clock modulator      
;
#set    CMPR            0x026F                  ; <<< Ref. to the data sheet, CMPR
; 
; Please  refer  to the data sheet  of the device  if you  enable clock modulation.  The 
; register CMPR dependant on the PLL-Clock.
;
; Note: If the CLKCAN source is set either to main oscillator or to PLL  output then the
;       clock  for  the CAN  is not influenced by  the clock  modulation.  If the CLKCAN 
;       source is set CPU clock (CLKB) then the clock for the CAN is also modulated  (if 
;       the clock modulator is enabled).
;
; Note: If the clock modulator is enabled,  the wait states  of the  internal flash wait 
;       states  must  be  adapted  to  maximum frequency.  Please check the  wait states 
;       settings.
;
; Note: This feature  is not supported by every device,  e.g. MB91461.  Please check the 
;       data sheet.
;
;=========================================================================================
; 4.8  External Bus Interface
;
;      The rest of the configuration is only applicable for devices with an external bus 
;      interface.
;
;      If the device does not offer an external bus interface,  the configuration can be 
;      stoped at this point.
;
;=========================================================================================
;
#set    EXTBUS          DEFAULT                 ; <<< Ext. Bus on/off
;
;                       ON      - The ext. bus interface is enabled and is configured as
;                                 set below. 
;                             
;                       OFF     - The ext. bus interface is  diabled.  The port function 
;                                 registers  are set to  general I/O.  The registers  of 
;                                 ext. bus interface will not be touched by the start-up 
;                                 file.  
;                                 Be aware, that the device  might be conifgured in ext.
;                                 bus mode by default after reset.
;
;                       DEFAULT - Neither the register nor the respective  port function
;                                 registers are touched by the start-up file.
;                                 Be aware, that the device  might be conifgured in ext. 
;                                 bus mode by default after reset.
;
;
; Note: This feature is not supported by every device. Please check the data sheet.  The 
;       following devices for example do not offer an external bus interface:  MB91464A, 
;       MB91467C, MB91465K, MB91463N, MB91465X.
;
;=========================================================================================
; 4.8.1  Select Chipselect (Only EXTBUS == ON)
;=========================================================================================
;
#set    CS0             OFF                     ; <<< select CS (ON/OFF)
#set    CS1             OFF                     ; <<< select CS (ON/OFF)
#set    CS2             OFF                     ; <<< select CS (ON/OFF)
#set    CS3             OFF                     ; <<< select CS (ON/OFF)
#set    CS4             OFF                     ; <<< select CS (ON/OFF)
#set    CS5             OFF                     ; <<< select CS (ON/OFF)
#set    CS6             OFF                     ; <<< select CS (ON/OFF)
#set    CS7             OFF                     ; <<< select CS (ON/OFF)
#set    SDRAM           OFF                     ; <<< select if a SDRAM is connected 
;
;
#set    ENACSX          B'00000000              ; <<< set CS, ENACSX
;                         ||||||||
;                         ||||||||__ CS0 bit, enable/disable CS0 (1/0)
;                         |||||||___ CS1 bit, enable/disable CS1 (1/0)
;                         ||||||____ CS2 bit, enable/disable CS2 (1/0)
;                         |||||_____ CS3 bit, enable/disable CS3 (1/0)
;                         ||||______ CS4 bit, enable/disable CS4 (1/0)
;                         |||_______ CS5 bit, enable/disable CS5 (1/0) 
;                         ||________ CS6 bit, enable/disable CS6 (1/0)
;                         |_________ CS7 bit, enable/disable CS7 (1/0)
;
; Note: If the SWB Monitor Debugger is used,  set the CS1 (external RAM only) or CS0 and 
;       CS 1 (external RAM and flash) to off.
;
; Note: Not all Chipselects  are supported by  the different devices.  Please check  the 
;       data sheet.
;
;=========================================================================================
; 4.8.2  Set memory addressing for Chipselects (only EXTBUS == ON)
;=========================================================================================
;
#set    AREASEL0        0x0000                  ; <<< set start add. for CS0, ASR0  
#set    AREASEL1        0x0000                  ; <<< set start add. for CS1, ASR1           
#set    AREASEL2        0x0000                  ; <<< set start add. for CS2, ASR2 
#set    AREASEL3        0x0000                  ; <<< set start add. for CS3, ASR3 
#set    AREASEL4        0x0000                  ; <<< set start add. for CS4, ASR4 
#set    AREASEL5        0x0000                  ; <<< set start add. for CS5, ASR5 
#set    AREASEL6        0x0000                  ; <<< set start add. for CS6, ASR6 
#set    AREASEL7        0x0000                  ; <<< set start add. for CS7, ASR7 
;
; Configure the starting address of each used Chipselect. Chipselects which are not used
; (not set to ON in "Select Chipselect") need not be set (setting ignored).
;
; NOTE: Just  the upper 16-bit  of the start address must be set,  e.g. when using start 
;       address 0x00080000 set 0x0008.
;
;=========================================================================================
; 4.8.3  Configure Chipselect Area (only EXTBUS == ON)
;=========================================================================================
;
#set    CONFIGCS0       B'0000000000000000      ; <<< Config. CS0, ACR0
#set    CONFIGCS1       B'0000000000000000      ; <<< Config. CS1, ACR1 
#set    CONFIGCS2       B'0000000000000000      ; <<< Config. CS2, ACR2 
#set    CONFIGCS3       B'0000000000000000      ; <<< Config. CS3, ACR3 
#set    CONFIGCS4       B'0000000000000000      ; <<< Config. CS4, ACR4  
#set    CONFIGCS5       B'0000000000000000      ; <<< Config. CS5, ACR5  
#set    CONFIGCS6       B'0000000000000000      ; <<< Config. CS6, ACR6  
#set    CONFIGCS7       B'0000000000000000      ; <<< Config. CS7, ACR7  
;                         ||||||||||||||||
;                         ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type
;                         |||||||||||||||___ TYP1 bit
;                         ||||||||||||||____ TYP2 bit
;                         |||||||||||||_____ TYP3 bit
;                         ||||||||||||______ LEND bit, select little '1' or big endian '0'
;                         |||||||||||_______ WREN bit, en-/disable (1/0) Write access
;                         ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch
;                         |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX
;                         ||||||||__________ BST0 bit, BSTx bits select burst size
;                         |||||||___________ BST1 bit
;                         ||||||____________ DBW0 bit, DBWx select data bus width
;                         |||||_____________ DBW1 bit
;                         ||||______________ ASZ0 bit, ASZx bits select address size of CS
;                         |||_______________ ASZ1 bit
;                         ||________________ ASZ2 bit
;                         |_________________ ASZ3 bit
;
; Bit description:
;
; TYP3 TYP2 TYP1 TYP0  : Select access type of each CS
; 0    0    X    X     : Normal access (asynchronous SRAM, I/O, 
;                        single/page/busrt-ROM/FLASH) 
; 0    1    X    X     : Address/data multiplexed (8bit / 16bit bus width only)
; 0    X    X    0     : WAIT insertion by RDY disabled
; 0    X    X    1     : WAIT insertion by RDY enabled
; 0    X    0    X     : The WR0X pin to the WR3X pin are used as write strobes 
;                        (WRX is fixed at H-Level)
; 0    X    1    X     : The WRX pin is used as write strobe 
; 1    0    0    0     : Memory type A: SDRAM/FCRAM (Auto pre-charge used)  
; 1    0    0    1     : Memory type B: FCRAM (Auto pre-charge used)  
; 1    0    1    0     : setting not allowed
; 1    0    1    1     : setting not allowed
; 1    1    0    0     : setting not allowed
; 1    1    0    1     : setting not allowed
; 1    1    1    0     : setting not allowed
; 1    1    1    1     : mask area setting
;
;               LEND   : select BYTE ordering 
;                0     : Big endian
;                1     : Little endian
;
;               WREN   : enable or disable write access 
;                0     : disabled 
;                1     : enabled,    
;
;               PFEN   : Enable or disable the pre-fetch
;                0     : disabled 
;                1     : enabled,    
;
;               SREN   : Enable or disable the sharing of BRQ and BGRNTX 
;                0     : disabled 
;                1     : enabled (CSx pin High-Z)
;
;          BST1 BST0   : set burst size of chip select area
;            0   0     : 1 burst (single access)
;            0   1     : 2 bursts (Address boundary 1 bit) 
;            1   0     : 4 bursts (Address boundary 2 bit)
;            1   1     : 8 bursts (Address boundary 3 bit)
;
;          DBW1 DBW0   : Set data bus width
;            0   0     : 8-bit (BYTE access)