crt0_str75x_freertos.s

FreeRTOS is a portable, open source, mini Real Time Kernel - a free to download and royalty free RTO

/*
This is the default Startup for STR75x devices for the GNU toolchain

It has been designed by ST Microelectronics and modified by Raisonance
and FreeRTOS.org.

You can use it, modify it, distribute it freely but without any waranty.

*/
.extern main

	   

/*; Depending on Your Application, Disable or Enable the following Defines*/
  /*; --------------------------------------------------------------------------
  ;                      SMI Bank0 configuration
; ----------------------------------------------------------------------------*/
.set SMI_Bank0_EN, 0 /*; enable access the SMI Bank0 if 1*/

/*; ----------------------------------------------------------------------------
  ;                      Memory remapping
; ----------------------------------------------------------------------------*/
.set Remap_SRAM, 0   /* remap SRAM at address 0x00 if 1 */
 
/*  ; ----------------------------------------------------------------------------
  ;                      EIC initialization
  ; ----------------------------------------------------------------------------*/
.set EIC_INIT, 1     /*; Configure and Initialize EIC if 1*/


;/* the following are useful for initializing the .data section */
.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata ;/* start address for the .data section. defined in linker script */
.extern _edata ;/* end address for the .data section. defined in linker script */

;/* the following are useful for initializing the .bss section */
.extern _sbss ;/* start address for the .bss section. defined in linker script */
.extern _ebss ;/* end address for the .bss section. defined in linker script */

;/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set  Mode_USR, 0x10            ;/* User Mode */
.set  Mode_FIQ, 0x11            ;/* FIQ Mode */
.set  Mode_IRQ, 0x12            ;/* IRQ Mode */
.set  Mode_SVC, 0x13            ;/* Supervisor Mode */
.set  Mode_ABT, 0x17            ;/* Abort Mode */
.set  Mode_UNDEF, 0x1B          ;/* Undefined Mode */
.set  Mode_SYS, 0x1F            ;/* System Mode */

.equ  I_Bit, 0x80               ;/* when I bit is set, IRQ is disabled */
.equ  F_Bit, 0x40               ;/* when F bit is set, FIQ is disabled */

/*; --- System memory locations */

;/* init value for the stack pointer. defined in linker script */
.extern _estack

;/* Stack Sizes. The default values are in the linker script, but they can be overriden. */
.extern _UND_Stack_Init
.extern _SVC_Stack_Init
.extern _ABT_Stack_Init
.extern _FIQ_Stack_Init
.extern _IRQ_Stack_Init
.extern _USR_Stack_Init

.extern _UND_Stack_Size
.extern _SVC_Stack_Size
.extern _ABT_Stack_Size
.extern _FIQ_Stack_Size
.extern _IRQ_Stack_Size
.extern _USR_Stack_Size
.extern vTaskSwitchContext
.extern ulCriticalNesting

SVC_Stack           =     _SVC_Stack_Init /*_estack*/           /*; 32 byte SVC stack at*/
                                              /*; top of memory */
                                              
IRQ_Stack           =     _IRQ_Stack_Init /*SVC_Stack - 32*/     /*; followed by IRQ stack */
USR_Stack           =     _USR_Stack_Init /*IRQ_Stack-256*/    /*; followed by USR stack */
FIQ_Stack           =     _FIQ_Stack_Init /*USR_Stack-256*/    /*; followed by FIQ stack*/
ABT_Stack           =     _ABT_Stack_Init /*FIQ_Stack-64*/     /*; followed by ABT stack */
UNDEF_Stack         =     _UND_Stack_Init /*ABT_Stack-0*/     /*; followed by UNDEF stack */

/*; --- System memory locations*/

/*; MRCC Register*/
MRCC_PCLKEN_Addr    =    0x60000030  /*; Peripheral Clock Enable register base address*/

/*; CFG Register*/
CFG_GLCONF_Addr     =    0x60000010  /*; Global Configuration register base address*/
SRAM_mask           =    0x0002      /*; to remap RAM at 0x0*/

/*; GPIO Register*/
GPIOREMAP0R_Addr    =    0xFFFFE420
SMI_EN_Mask         =    0x00000001

/*; SMI Register*/
SMI_CR1_Addr        =    0x90000000

/*; --- Stack Addres for each ARM mode*/
/*; add FIQ_Stack, ABT_Stack, UNDEF_Stack here if you need them*/


/*; --- EIC Registers offsets*/
EIC_base_addr       =    0xFFFFF800         /*; EIC base address*/
ICR_off_addr        =    0x00               /*; Interrupt Control register offset*/
CICR_off_addr       =    0x04               /*; Current Interrupt Channel Register*/
CIPR_off_addr       =    0x08               /*; Current Interrupt Priority Register offset*/
IVR_off_addr        =    0x18               /*; Interrupt Vector Register offset*/
FIR_off_addr        =    0x1C               /*; Fast Interrupt Register offset*/
IER_off_addr        =    0x20               /*; Interrupt Enable Register offset*/
IPR_off_addr        =    0x40               /*; Interrupt Pending Bit Register offset*/
SIR0_off_addr       =    0x60               /*; Source Interrupt Register 0*/

/***************************************************************************************/


.globl _start
.globl _startup

.text
_startup:
_start:
        LDR     PC, Reset_Addr
        LDR     PC, Undefined_Addr
        LDR     PC, SWI_Addr
        LDR     PC, Prefetch_Addr
        LDR     PC, Abort_Addr
        NOP                          /*; Reserved vector*/
        LDR     PC, IRQ_Addr
        LDR     PC, FIQ_Addr





Reset_Addr      : .long     Reset_Handler
Undefined_Addr  : .long     UndefinedHandler
SWI_Addr        : .long     SWIHandler
Prefetch_Addr   : .long     PrefetchAbortHandler
Abort_Addr      : .long     DataAbortHandler
                  .long 0      /*; Reserved vector*/
IRQ_Addr        : .long     IRQHandler
FIQ_Addr        : .long     FIQHandler

.text
/*;*******************************************************************************
;              Peripherals IRQ handlers address table
;********************************************************************************/

/* execution goes there when an interrupt occurs and there is no associated ISR */
.globl __wrongvector
__wrongvector:
	ldr     PC, __wrongvector_Addr	
__wrongvector_Addr:
	.long 0

WAKUP_Addr         :.long	WAKUPIRQHandler
TIM2_OC2_Addr      :.long	TIM2_OC2IRQHandler
TIM2_OC1_Addr      :.long	TIM2_OC1IRQHandler
TIM2_IC12_Addr     :.long	TIM2_IC12IRQHandler
TIM2_UP_Addr       :.long	TIM2_UPIRQHandler
TIM1_OC2_Addr      :.long	TIM1_OC2IRQHandler
TIM1_OC1_Addr      :.long	TIM1_OC1IRQHandler
TIM1_IC12_Addr     :.long	TIM1_IC12IRQHandler
TIM1_UP_Addr       :.long	TIM1_UPIRQHandler
TIM0_OC2_Addr      :.long	TIM0_OC2IRQHandler
TIM0_OC1_Addr      :.long	TIM0_OC1IRQHandler
TIM0_IC12_Addr     :.long	TIM0_IC12IRQHandler
TIM0_UP_Addr       :.long	TIM0_UPIRQHandler
PWM_OC123_Addr     :.long	PWM_OC123IRQHandler
PWM_EM_Addr        :.long	PWM_EMIRQHandler
PWM_UP_Addr        :.long	PWM_UPIRQHandler
I2C_Addr           :.long	I2CIRQHandler
SSP1_Addr          :.long	SSP1IRQHandler
SSP0_Addr          :.long	SSP0IRQHandler
UART2_Addr         :.long	UART2IRQHandler
UART1_Addr         :.long	UART1IRQHandler
UART0_Addr         :.long	vSerialISR
CAN_Addr           :.long	CANIRQHandler
USB_LP_Addr        :.long	USB_LPIRQHandler
USB_HP_Addr        :.long	USB_HPIRQHandler
ADC_Addr           :.long	ADCIRQHandler
DMA_Addr           :.long	DMAIRQHandler
EXTIT_Addr         :.long	EXTITIRQHandler
MRCC_Addr          :.long	MRCCIRQHandler
FLASHSMI_Addr      :.long	FLASHSMIIRQHandler
RTC_Addr           :.long	RTCIRQHandler
TB_Addr            :.long	vPortTickISR

/*;*******************************************************************************
;                         Exception Handlers
;********************************************************************************/


/*;*******************************************************************************
;* FreeRTOS.org macros for saving and restoring a task context
;*******************************************************************************/

	.macro portSAVE_CONTEXT MACRO

	/* ; Push R0 as we are going to use the register. */
	STMDB	SP!, {R0}

	/* ; Set R0 to point to the task stack pointer. */
	STMDB	SP, {SP}^
	NOP
	SUB		SP, SP, #4
	LDMIA	SP!, {R0}

	/* ; Push the return address onto the stack. 	*/
	STMDB	R0!, {LR}

	/* ; Now we have saved LR we can use it instead of R0. 	*/
	MOV		LR, R0

	/* ; Pop R0 so we can save it onto the system mode stack. */
	LDMIA	SP!, {R0}

	/* ; Push all the system mode registers onto the task stack. */
	STMDB	LR, {R0-LR}^
	NOP
	SUB		LR, LR, #60

	/* ; Push the SPSR onto the task stack.  */
	MRS		R0, SPSR
	STMDB	LR!, {R0}

	LDR		R0, =ulCriticalNesting 
	LDR		R0, [R0]
	STMDB	LR!, {R0}

	/* ; Store the new top of stack for the task. 	*/
	LDR		R1, =pxCurrentTCB
	LDR		R0, [R1]
	STR		LR, [R0]

	.endm


	.macro portRESTORE_CONTEXT MACRO

	/* ; Set the LR to the task stack. 	*/
	LDR		R1, =pxCurrentTCB
	LDR		R0, [R1]
	LDR		LR, [R0]

	/* ; The critical nesting depth is the first item on the stack. 	
	; Load it into the ulCriticalNesting variable. 	*/
	LDR		R0, =ulCriticalNesting
	LDMFD	LR!, {R1}
	STR		R1, [R0]

	/* ; Get the SPSR from the stack. 	*/
	LDMFD	LR!, {R0}
	MSR		SPSR_cxsf, R0

	/* ; Restore all system mode registers for the task. */
	LDMFD	LR, {R0-R14}^
	NOP

	/* ; Restore the return address. */
	LDR		LR, [LR, #+60]

	/* ; And return - correcting the offset in the LR to obtain the 	
	; correct address. 	*/
	SUBS	PC, LR, #4
	
	.endm



/*;*******************************************************************************
;* Macro Name     : SaveContext
;* Description    : This macro used to save the context before entering
;                   an exception handler.
;* Input          : The range of registers to store.
;* Output         : none
;********************************************************************************/

       .macro SaveContext $r0,$r12
        STMFD  sp!,{r0-r12,lr} /*; Save The workspace plus the current return*/
                               /*; address lr_ mode into the stack.*/
        MRS    r1,spsr         /*; Save the spsr_mode into r1.*/
        STMFD  sp!,{r1}        /*; Save spsr.*/
        .endm

/*;*******************************************************************************
;* Macro Name     : RestoreContext
;* Description    : This macro used to restore the context to return from
;                   an exception handler and continue the program execution.
;* Input          : The range of registers to restore.
;* Output         : none
;********************************************************************************/

        .macro RestoreContext $r0,$r12
        LDMFD   sp!,{r1}        /*; Restore the saved spsr_mode into r1.*/
        MSR     spsr_cxsf,r1    /*; Restore spsr_mode.*/
        LDMFD   sp!,{r0-r12,pc}^/*; Return to the instruction following...*/
                                /*; ...the exception interrupt.*/
        .endm



/*;*******************************************************************************
;* Function Name  : UndefinedHandler
;* Description    : This function called when undefined instruction
;                   exception is entered.
;* Input          : none
;* Output         : none
;*********************************************************************************/

UndefinedHandler:
        SaveContext r0,r12    /*; Save the workspace plus the current*/
                              /*; return address lr_ und and spsr_und.*/
        BL      Undefined_Handler/*; Branch to Undefined_Handler*/
        RestoreContext r0,r12 /*; Return to the instruction following...*/
                              /*; ...the undefined instruction.*/

/*;*******************************************************************************
;* Function Name  : SWIHandler
;* Description    : This function called when SWI instruction executed.
;* Input          : none
;* Output         : none
;********************************************************************************/

SWIHandler:
		ADD	LR, LR, #4
        portSAVE_CONTEXT        
        LDR R0, =vTaskSwitchContext
        MOV LR, PC
        BX R0
        portRESTORE_CONTEXT 


/*;*******************************************************************************
;* Function Name  : IRQHandler
;* Description    : This function called when IRQ exception is entered.
;* Input          : none
;* Output         : none
;********************************************************************************/


IRQHandler:

	portSAVE_CONTEXT					/*; Save the context of the current task. */

	LDR    r0, =EIC_base_addr
	LDR    r1, =IVR_off_addr
	LDR    lr, =ReturnAddress			/*; Load the return address. */
	ADD    pc,r0,r1						/*; Branch to the IRQ handler. */
ReturnAddress:
	LDR    r0, =EIC_base_addr
	LDR    r2, [r0, #CICR_off_addr]		/*; Get the IRQ channel number. */
	MOV    r3,#1