iolpc2138.h

NXPLPC2138 平台下使用UC/0S-II 操作系統. 在IAR工工程環境下的源代碼.帶有一此驅動程序,LCD驅動,還有原開發板的BSP包.

/* TIMER count control register */
typedef struct{
__REG32 CTM : 2;     //Counter/Timer Mode
__REG32 CIS : 2;     //Count Input Select
__REG32     :28;
} __ctcr_bits;

/* TIMER match control register */
typedef struct{
__REG32 MR0INT   : 1;
__REG32 MR0RES   : 1;
__REG32 MR0STOP  : 1;
__REG32 MR1INT   : 1;
__REG32 MR1RES   : 1;
__REG32 MR1STOP  : 1;
__REG32 MR2INT   : 1;
__REG32 MR2RES   : 1;
__REG32 MR2STOP  : 1;
__REG32 MR3INT   : 1;
__REG32 MR3RES   : 1;
__REG32 MR3STOP  : 1;
__REG32          :20;
} __mcr_bits;

/* TIMER capture control register */
typedef struct{
__REG32 CAP0RE   : 1;
__REG32 CAP0FE   : 1;
__REG32 CAP0INT  : 1;
__REG32 CAP1RE   : 1;
__REG32 CAP1FE   : 1;
__REG32 CAP1INT  : 1;
__REG32 CAP2RE   : 1;
__REG32 CAP2FE   : 1;
__REG32 CAP2INT  : 1;
__REG32 CAP3RE   : 1;
__REG32 CAP3FE   : 1;
__REG32 CAP3INT  : 1;
__REG32          :20;
} __ccr_bits;

/* TIMER external match register */
typedef struct{
__REG32 EM0   : 1;
__REG32 EM1   : 1;
__REG32 EM2   : 1;
__REG32 EM3   : 1;
__REG32 EMC0  : 2;
__REG32 EMC1  : 2;
__REG32 EMC2  : 2;
__REG32 EMC3  : 2;
__REG32       :20;
} __emr_bits;

/* PWM interrupt register */
typedef struct{
__REG32 MR0INT  : 1;
__REG32 MR1INT  : 1;
__REG32 MR2INT  : 1;
__REG32 MR3INT  : 1;
__REG32         : 4;
__REG32 MR4INT  : 1;
__REG32 MR5INT  : 1;
__REG32 MR6INT  : 1;
__REG32         :21;
} __pwmir_bits;

/* PWM timer control register */
typedef struct{
__REG32 CE     : 1;
__REG32 CR     : 1;
__REG32        : 1;
__REG32 PWMEN  : 1;
__REG32        :28;
} __pwmtcr_bits;

/* PWM match control register */
typedef struct{
__REG32 MR0INT   : 1;
__REG32 MR0RES   : 1;
__REG32 MR0STOP  : 1;
__REG32 MR1INT   : 1;
__REG32 MR1RES   : 1;
__REG32 MR1STOP  : 1;
__REG32 MR2INT   : 1;
__REG32 MR2RES   : 1;
__REG32 MR2STOP  : 1;
__REG32 MR3INT   : 1;
__REG32 MR3RES   : 1;
__REG32 MR3STOP  : 1;
__REG32 MR4INT   : 1;
__REG32 MR4RES   : 1;
__REG32 MR4STOP  : 1;
__REG32 MR5INT   : 1;
__REG32 MR5RES   : 1;
__REG32 MR5STOP  : 1;
__REG32 MR6INT   : 1;
__REG32 MR6RES   : 1;
__REG32 MR6STOP  : 1;
__REG32          :11;
} __pwmmcr_bits;

/* PWM  control register */
typedef struct{
__REG32       : 1;
__REG32 SEL1  : 1;
__REG32 SEL2  : 1;
__REG32 SEL3  : 1;
__REG32 SEL4  : 1;
__REG32 SEL5  : 1;
__REG32 SEL6  : 1;
__REG32       : 2;
__REG32 ENA1  : 1;
__REG32 ENA2  : 1;
__REG32 ENA3  : 1;
__REG32 ENA4  : 1;
__REG32 ENA5  : 1;
__REG32 ENA6  : 1;
__REG32       :17;
} __pwmpcr_bits;

/* PWM latch enable register */
typedef struct{
__REG32 EM0L  : 1;
__REG32 EM1L  : 1;
__REG32 EM2L  : 1;
__REG32 EM3L  : 1;
__REG32 EM4L  : 1;
__REG32 EM5L  : 1;
__REG32 EM6L  : 1;
__REG32       :25;
} __pwmler_bits;

/* A/D control register */
typedef struct{
__REG32 SEL     : 8;
__REG32 CLKDIV  : 8;
__REG32 BURST   : 1;
__REG32 CLKS    : 3;
__REG32         : 1;
__REG32 PDN     : 1;
__REG32 TEST    : 2;
__REG32 START   : 3;
__REG32 EDGE    : 1;
__REG32         : 4;
} __adcr_bits;

/* A/D data register */
typedef struct{
__REG32         : 6;
__REG32 RESULT  :10;
__REG32         : 8;
__REG32 CHN     : 3;
__REG32         : 3;
__REG32 OVERUN  : 1;
__REG32 DONE    : 1;
} __adgdr_bits;

/* A/D Global Start Register */
typedef struct{
__REG32        :16;
__REG32 BURST  : 1;
__REG32        : 7;
__REG32 START  : 3;
__REG32 EDGE   : 1;
__REG32        : 4;
} __adgsr_bits;

/* A/D Status Register */
typedef struct{
__REG32 DONE0     : 1;
__REG32 DONE1     : 1;
__REG32 DONE2     : 1;
__REG32 DONE3     : 1;
__REG32 DONE4     : 1;
__REG32 DONE5     : 1;
__REG32 DONE6     : 1;
__REG32 DONE7     : 1;
__REG32 OVERRUN0  : 1;
__REG32 OVERRUN1  : 1;
__REG32 OVERRUN2  : 1;
__REG32 OVERRUN3  : 1;
__REG32 OVERRUN4  : 1;
__REG32 OVERRUN5  : 1;
__REG32 OVERRUN6  : 1;
__REG32 OVERRUN7  : 1;
__REG32 ADINT     : 1;
__REG32           :15;
} __adstat_bits;

/* A/D Status Register */
typedef struct{
__REG32 ADINTEN0  : 1;
__REG32 ADINTEN1  : 1;
__REG32 ADINTEN2  : 1;
__REG32 ADINTEN3  : 1;
__REG32 ADINTEN4  : 1;
__REG32 ADINTEN5  : 1;
__REG32 ADINTEN6  : 1;
__REG32 ADINTEN7  : 1;
__REG32 ADINTEN   : 1;
__REG32           :23;
} __adinten_bits;

/* A/D Data Register */
typedef struct{
__REG32         : 6;
__REG32 RESULT  :10;
__REG32         :14;
__REG32 OVERUN  : 1;
__REG32 DONE    : 1;
} __addr_bits;

/* D/A Converter Register */
typedef struct{
__REG32        : 6;
__REG32 VALUE  :10;
__REG32 BIAS   : 1;
__REG32        :15;
} __dacr_bits;

/* RTC interrupt location register */
typedef struct{
__REG32 RTCCIF  : 1;
__REG32 RTCALF  : 1;
__REG32         :30;
} __ilr_bits;

/* RTC clock tick counter register */
typedef struct{
__REG32          : 1;
__REG32 COUNTER  :15;
__REG32          :16;
} __ctc_bits;

/* RTC clock control register */
typedef struct{
__REG32 CLKEN   : 1;
__REG32 CTCRST  : 1;
__REG32 CTTEST  : 2;
__REG32 CLKSRC  : 1;
__REG32         :27;
} __rtcccr_bits;

/* RTC counter increment interrupt register */
typedef struct{
__REG32 IMSEC   : 1;
__REG32 IMMIN   : 1;
__REG32 IMHOUR  : 1;
__REG32 IMDOM   : 1;
__REG32 IMDOW   : 1;
__REG32 IMDOY   : 1;
__REG32 IMMON   : 1;
__REG32 IMYEAR  : 1;
__REG32         :24;
} __ciir_bits;

/* RTC alarm mask register */
typedef struct{
__REG32 AMRSEC   : 1;
__REG32 AMRMIN   : 1;
__REG32 AMRHOUR  : 1;
__REG32 AMRDOM   : 1;
__REG32 AMRDOW   : 1;
__REG32 AMRDOY   : 1;
__REG32 AMRMON   : 1;
__REG32 AMRYEAR  : 1;
__REG32          :24;
} __amr_bits;

/* RTC consolidated time register 0 */
typedef struct{
__REG32 SEC   : 6;
__REG32       : 2;
__REG32 MIN   : 6;
__REG32       : 2;
__REG32 HOUR  : 5;
__REG32       : 3;
__REG32 DOW   : 3;
__REG32       : 5;
} __ctime0_bits;

/* RTC consolidated time register 1 */
typedef struct{
__REG32 DOM   : 5;
__REG32       : 3;
__REG32 MON   : 4;
__REG32       : 4;
__REG32 YEAR  :12;
__REG32       : 4;
} __ctime1_bits;

/* RTC consolidated time register 2 */
typedef struct{
__REG32 DOY  :12;
__REG32      :20;
} __ctime2_bits;

/* RTC second register */
typedef struct{
__REG32 SEC  : 6;
__REG32      :26;
} __sec_bits;

/* RTC minute register */
typedef struct{
__REG32 MIN  : 6;
__REG32      :26;
} __min_bits;

/* RTC hour register */
typedef struct{
__REG32 HOUR  : 5;
__REG32       :27;
} __hour_bits;

/* RTC day of month register */
typedef struct{
__REG32 DOM  : 5;
__REG32      :27;
} __dom_bits;

/* RTC day of week register */
typedef struct{
__REG32 DOW  : 3;
__REG32      :29;
} __dow_bits;

/* RTC day of year register */
typedef struct{
__REG32 DOY  : 9;
__REG32      :23;
} __doy_bits;

/* RTC month register */
typedef struct{
__REG32 MON  : 4;
__REG32      :28;
} __month_bits;

/* RTC year register */
typedef struct{
__REG32 YEAR  :12;
__REG32       :20;
} __year_bits;

/* RTC prescaler value, integer portion register */
typedef struct{
__REG32 VALUE  :13;
__REG32        :19;
} __preint_bits;

/* RTC prescaler value, fractional portion register */
typedef struct{
__REG32 VALUE  :15;
__REG32        :17;
} __prefrac_bits;

/* Watchdog mode register */
typedef struct{
__REG32 WDEN     : 1;
__REG32 WDRESET  : 1;
__REG32 WDTOF    : 1;
__REG32 WDINT    : 1;
__REG32          :28;
} __wdmod_bits;

/* Watchdog feed register */
typedef struct{
__REG32 FEED  : 8;
__REG32       :24;
} __wdfeed_bits;

#endif    /* __IAR_SYSTEMS_ICC__ */

/* Common declarations  ****************************************************/

/***************************************************************************
 **
 ** System control block
 **
 ***************************************************************************/
__IO_REG32_BIT(EXTINT,          0xE01FC140,__READ_WRITE,__extint_bits);
__IO_REG32_BIT(EXTWAKE,         0xE01FC144,__READ_WRITE,__extwake_bits);
__IO_REG32_BIT(EXTMODE,         0xE01FC148,__READ_WRITE,__extmode_bits);
__IO_REG32_BIT(EXTPOLAR,        0xE01FC14C,__READ_WRITE,__extpolar_bits);
__IO_REG32_BIT(MEMMAP,          0xE01FC040,__READ_WRITE,__memmap_bits);
__IO_REG32_BIT(PLLCON,          0xE01FC080,__READ_WRITE,__pllcon_bits);
__IO_REG32_BIT(PLLCFG,          0xE01FC084,__READ_WRITE,__pllcfg_bits);
__IO_REG32_BIT(PLLSTAT,         0xE01FC088,__READ      ,__pllstat_bits);
__IO_REG32_BIT(PLLFEED,         0xE01FC08C,__WRITE     ,__pllfeed_bits);
__IO_REG32_BIT(PCON,            0xE01FC0C0,__READ_WRITE,__pcon_bits);
__IO_REG32_BIT(PCONP,           0xE01FC0C4,__READ_WRITE,__pconp_bits);
__IO_REG32_BIT(VPBDIV,          0xE01FC100,__READ_WRITE,__vpbdiv_bits);
__IO_REG32_BIT(RSIR,            0xE01FC180,__READ_WRITE,__rsir_bits);
__IO_REG32(    SCCSPR,          0xE01FC184,__READ_WRITE);

/***************************************************************************
 **
 ** MAM
 **
 ***************************************************************************/
__IO_REG32_BIT(MAMCR,  0xE01FC000,__READ_WRITE,__mamcr_bits);
__IO_REG32_BIT(MAMTIM, 0xE01FC004,__READ_WRITE,__mamtim_bits);

/***************************************************************************
 **
 ** VIC
 **
 ***************************************************************************/
__IO_REG32_BIT(VICIRQStatus,    0xFFFFF000,__READ      ,__vicint_bits);
__IO_REG32_BIT(VICFIQStatus,    0xFFFFF004,__READ      ,__vicint_bits);
__IO_REG32_BIT(VICRawIntr,      0xFFFFF008,__READ      ,__vicint_bits);
__IO_REG32_BIT(VICIntSelect,    0xFFFFF00C,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnable,    0xFFFFF010,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnClear,   0xFFFFF014,__WRITE     ,__vicint_bits);
__IO_REG32_BIT(VICSoftInt,      0xFFFFF018,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICSoftIntClear, 0xFFFFF01C,__WRITE     ,__vicint_bits);
__IO_REG32_BIT(VICProtection,   0xFFFFF020,__READ_WRITE,__vicprotection_bits);
__IO_REG32(    VICVectAddr,     0xFFFFF030,__READ_WRITE);
__IO_REG32(    VICDefVectAddr,  0xFFFFF034,__READ_WRITE);
__IO_REG32(    VICVectAddr0,    0xFFFFF100,__READ_WRITE);
__IO_REG32(    VICVectAddr1,    0xFFFFF104,__READ_WRITE);
__IO_REG32(    VICVectAddr2,    0xFFFFF108,__READ_WRITE);
__IO_REG32(    VICVectAddr3,    0xFFFFF10C,__READ_WRITE);
__IO_REG32(    VICVectAddr4,    0xFFFFF110,__READ_WRITE);
__IO_REG32(    VICVectAddr5,    0xFFFFF114,__READ_WRITE);
__IO_REG32(    VICVectAddr6,    0xFFFFF118,__READ_WRITE);
__IO_REG32(    VICVectAddr7,    0xFFFFF11C,__READ_WRITE);
__IO_REG32(    VICVectAddr8,    0xFFFFF120,__READ_WRITE);
__IO_REG32(    VICVectAddr9,    0xFFFFF124,__READ_WRITE);
__IO_REG32(    VICVectAddr10,   0xFFFFF128,__READ_WRITE);
__IO_REG32(    VICVectAddr11,   0xFFFFF12C,__READ_WRITE);
__IO_REG32(    VICVectAddr12,   0xFFFFF130,__READ_WRITE);
__IO_REG32(    VICVectAddr13,   0xFFFFF134,__READ_WRITE);
__IO_REG32(    VICVectAddr14,   0xFFFFF138,__READ_WRITE);
__IO_REG32(    VICVectAddr15,   0xFFFFF13C,__READ_WRITE);
__IO_REG32_BIT(VICVectCntl0,    0xFFFFF200,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl1,    0xFFFFF204,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl2,    0xFFFFF208,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl3,    0xFFFFF20C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl4,    0xFFFFF210,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl5,    0xFFFFF214,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl6,    0xFFFFF218,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl7,    0xFFFFF21C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl8,    0xFFFFF220,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl9,    0xFFFFF224,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl10,   0xFFFFF228,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl11,   0xFFFFF22C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl12,   0xFFFFF230,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl13,   0xFFFFF234,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl14,   0xFFFFF238,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl15,   0xFFFFF23C,__READ_WRITE,__vicvectcntl_bits);

/***************************************************************************
 **
 ** Pin connect block
 **
 ***************************************************************************/
__IO_REG32_BIT(PINSEL0,         0xE002C000,__READ_WRITE,__pinsel0_bits);
__IO_REG32_BIT(PINSEL1,         0xE002C004,__READ_WRITE,__pinsel1_bits);
__IO_REG32(    PINSEL2,         0xE002C014,__READ_WRITE);

/***************************************************************************
 **
 ** GPIO
 **
 ***************************************************************************/
__IO_REG32_BIT(IO0PIN,          0xE0028000,__READ_WRITE,__gpio0_bits);