syslib.c

workbench下vxworks6.6的ARM920T核对应的BSP源码

/* sysLib.c - ARM Integrator system-dependent routines */

/* Copyright 1999-2003 ARM Limited */
/*
 * Copyright (c) 1999-2007 Wind River Systems, Inc.
 *
 * The right to copy, distribute or otherwise make use of this software
 * may be licensed only pursuant to the terms of an applicable Wind River
 * license agreement.
 */

/*
modification history
--------------------
02f,26sep07,mdo  Clear out apigen errors/warnings
02e,08aug07,agf  remove duplicate variable definitions
02d,07mar06,jmt  Use SYS_MODEL to define sysModel string
02c,15aug05,h_k  added INCLUDE_MMU_GLOBAL_MAP support.
02b,20jul05,h_k  corrected _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK conditions.
02a,08jul05,h_k  cleaned up decoupling.
01z,29mar05,jb   Adding 1136jfs support
01y,24feb05,rec  lock interrupts when rebooting SPR-102682
01x,17feb05,rec  fix compiler warning
01w,03feb05,rec  fix return value for sysMemTop
01v,17jan05,rec  base6 update - memTop computation
01u,29oct04,rec  support no network builds
01t,28oct04,rec  pass translation functions to cach lib install
01s,12aug04,scm  add 926E support...
01r,29may03,rec  Power Management
01w,25feb03,jb   Enabling access to Private SDRAM
01v,04feb03,jb   Adding ARM10 Support
01r,21jan03,jb   Resolving SPR 81285
01q,28may02,m_h  windML not UGL
01p,31oct01,rec  use generic driver for amba timer
01o,09oct01,m_h  configure keyboard if windML is configured
01n,09oct01,jpd  correct sysPhysMemDesc entres for 946es.
01m,03oct01,jpd  tidied slightly
01l,28sep01,pr   added support for ARM946E.
01k,12sep01,m_h  WindML support
01j,27aug01,jb   Adding USB support
01i,21feb01,h_k  added support for ARM966ES and ARM966ES_T.
01h,01dec00,rec  fix typo in INCLUDE_FEI82557END
01g,20nov00,jpd  added support for Intel Ethernet driver.
01f,14jun00,pr   fixed Flash enable/disable with recent versions of FPGA.
01e,18feb00,jpd  minor tidying. Added Core Module Header sysPhysMemDesc entry.
01d,07feb00,jpd  added support for ARM720T, ARM920T.
01c,13jan00,pr	 added support for ARM740T.
01b,07dec99,pr	 added support for PCI.
01a,15nov99,ajb  copied from pid7t version 01o.
*/

/*
DESCRIPTION
This library provides board-specific routines for the ARM Integrator
Development Board BSP.

It #includes the following chip drivers:
    nullVme.c -         dummy VMEbus routines
    ambaTimer.c -       AMBA timer driver
    ambaIntrCtl.c -     AMBA interrupt controller driver
    primeCellSio.c -	PrimeCell UART driver
    pciIomapLib.c -	PCI I/O mapping support
if INCLUDE_FLASH is defined, it #includes:
    flashMem.c -        Flash memory driver
    nvRamToFlash.c -    driver to use some Flash like NVRAM
else it #includes:
    nullNvRam.c -	dummy NVRAM routines

It #includes the following BSP files:
    sysSerial.c -	serial device initialization routines
    sysEnd.c -		END network driver support routines.
    pciIomapShow.c -	PCI Show routines

INCLUDE FILES: sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h
	       pciIomapLib.h

SEE ALSO:
\tb VxWorks Programmer's Guide: Configuration
\tb "ARM Architecture Reference Manual,"
\tb "ARM 7TDMI Data Sheet,"
\tb "ARM 720T Data Sheet,"
\tb "ARM 740T Data Sheet,"
\tb "ARM 920T Technical Reference Manual",
\tb "ARM 940T Technical Reference Manual",
\tb "ARM 926E-S Technical Reference Manual",
\tb "ARM 946E-S Technical Reference Manual",
\tb "ARM 966E-S Technical Reference Manual",
\tb "ARM 1020E Technical Reference Manual",
\tb "ARM 1022E Technical Reference Manual",
\tb "ARM 1136JF-S Technical Reference Manual",
\tb "ARM Reference Peripherals Specification,"
\tb "ARM Integrator/AP User Guide",
\tb "ARM Integrator/CM7TDMI User Guide",
\tb "ARM Integrator/CM720T User Guide",
\tb "ARM Integrator/CM740T User Guide",
\tb "ARM Integrator/CM920T User Guide",
\tb "ARM Integrator/CM926EJ-S User Guide",
\tb "ARM Integrator/CM940T User Guide",
\tb "ARM Integrator/CM946E User Guide",
\tb "ARM Integrator/CM9x6ES Datasheet".
\tb "ARM Integrator/CM10200 User Guide",
\tb "ARM Integrator/CM1136JF-S User Guide",
*/

/* includes */

#include <vxWorks.h>
#include "config.h"

#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU) || \
     defined(INCLUDE_MMU_GLOBAL_MAP))
#define INCLUDE_MMU
#endif

#include <sysLib.h>
#include <string.h>
#include <intLib.h>
#include <taskLib.h>
#include <vxLib.h>
#include <muxLib.h>
#include <cacheLib.h>
#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)
#ifdef	INCLUDE_MMU
#include <arch/arm/mmuArmLib.h>
#include <private/vmLibP.h>
#endif	/* INCLUDE_MMU */
#include <dllLib.h>
#include "pciIomapLib.h"
#endif /* defined(720T/740T/920T/926E/940T/946ES/1020E/1022E/CPU_1136JF) */

#ifdef INCLUDE_WINDML
#define INCLUDE_AMBAKEYBOARD
#define INCLUDE_AMBAMOUSE
#endif

/* imports */

IMPORT char end [];			    /* end of system, created by ld */
#ifndef	_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */
#endif	/* !_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */

#if defined(INCLUDE_CACHE_SUPPORT)
#if defined(CPU_7TDMI) || defined(CPU_7TDMI_T) || \
    defined(CPU_966ES) || defined(CPU_966ES_T)
       FUNCPTR sysCacheLibInit = NULL;
#endif /* defined(CPU_7TDMI/7TDMI_T) */

#if defined(CPU_940T) || defined(CPU_940T_T) || \
    defined (CPU_926E) || defined(CPU_926E_T)
UINT32 * sysCacheUncachedAdrs = (UINT32 *)SYS_CACHE_UNCACHED_ADRS;
#endif /* defined(CPU_940T/940T_T) */
#endif /* defined(INCLUDE_CACHE_SUPPORT) */

/* globals */

#if defined(INCLUDE_MMU)

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)  || \
    defined(CPU_1136JF)

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_926E) || defined(CPU_926E_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)  || \
    defined(CPU_1136JF)

/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialization by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL/GLOBAL_MAP are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    /* DRAM must always be the first entry */
    /* adrs and length parameters must be page-aligned (multiples of 0x1000) */
    /* DRAM - Always the first entry */
    {
    LOCAL_MEM_LOCAL_ADRS,	/* virtual address */
    LOCAL_MEM_LOCAL_ADRS,	/* physical address */
    ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
    },

#if defined(CPU_1020E) || defined(CPU_1022E)
    /* If (e.g. on 10200) we have image starting above where the
     * tightly-coupled memory is, then put another entry (higher priority than
     * the one before), which marks the area taken up by the tightly-coupled
     * memory as non-cacheable.
     */

    /* on-header SSRAM, or tightly-coupled memory */
    /* This should always be the second entry in sysPhysMemDesc */
    {
    INTEGRATOR_SSRAM_BASE,	/* virtual address */
    INTEGRATOR_SSRAM_BASE,	/* physical address */
    INTEGRATOR_HDR_SSRAM_SIZE, /* length, then initial state */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*
     * Private SDRAM - 64 MB. The CM10200/CM10220's private sdram.
     */
    {
    INTEGRATOR_HDR_PVT_SDRAM_BASE,	/* virtual address */
    INTEGRATOR_HDR_PVT_SDRAM_BASE,	/* physical address */
    ROUND_UP (INTEGRATOR_HDR_PVT_SDRAM_SIZE, PAGE_SIZE), /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
    },


#endif /* defined(CPU_1020E) || defined(CPU_1022E) */

    /*
     * ROM is normally marked as uncacheable by VxWorks. We leave it like that
     * for the time being, even though this has a severe impact on execution
     * speed from ROM.
     */
    {
    ROM_BASE_ADRS,
    ROM_BASE_ADRS,
    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
#ifdef INCLUDE_FLASH
    /* needs to be writable */

    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
#else
    VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
#endif
    },

    /*
     * I/O space:
     * Do not map in all I/O space, only that which has something there.
     * Otherwise we will use all of RAM allocating page tables!
     */
    {
    INTEGRATOR_HDR_BASE,	/* Core Module Header regs */
    INTEGRATOR_HDR_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    INTEGRATOR_SC_BASE,	/* System controller */
    INTEGRATOR_SC_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    INTEGRATOR_EBI_BASE,	/* EBI controller */
    INTEGRATOR_EBI_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#if defined(INCLUDE_TTY_DEV) || defined(INCLUDE_SIO_POLL)
    {
    UART_0_BASE_ADR,		/* PrimeCell UART */
    UART_0_BASE_ADR,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    UART_1_BASE_ADR,		/* PrimeCell UART */
    UART_1_BASE_ADR,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_TTY_DEV || INCLUDE_SIO_POLL */
#ifdef INCLUDE_AMBAKEYBOARD
    {
    KBD_BASE_ADR,		/* PrimeCell Keyboard */
    KBD_BASE_ADR,
    ROUND_UP (KBD_REGS_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_AMBAKEYBOARD */
#ifdef INCLUDE_AMBAMOUSE
    {
    MOUSE_BASE_ADR,		/* PrimeCell Mouse */
    MOUSE_BASE_ADR,
    ROUND_UP (MOUSE_REGS_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_AMBAMOUSE */
    {
    IC_BASE,		/* Interrupt controller */
    IC_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    AMBA_TIMER_BASE,	/* Counter/Timer */
    AMBA_TIMER_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    LED_BASE,		/* LEDs */
    LED_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#ifdef INCLUDE_PCI
    {
    CPU_PCI_IO_ADRS,	/* PCI I/O space */
    CPU_PCI_IO_ADRS,
    ROUND_UP (CPU_PCI_IO_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    CPU_PCI_CNFG_ADRS,	/* PCI Configuration space */
    CPU_PCI_CNFG_ADRS,
    ROUND_UP (CPU_PCI_CNFG_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#ifdef INTEGRATOR_CONSERVE_VIRTUAL_SPACE
    /* Conserve mmu table space and overhead */
    {
    CPU_PCI_MEM_ADRS,	/* PCI Mem space */
    CPU_PCI_MEM_ADRS,
    ROUND_UP (SZ_8M, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#else
    {
    CPU_PCI_MEM_ADRS,	/* PCI Mem space */
    CPU_PCI_MEM_ADRS,
    ROUND_UP (CPU_PCI_MEM_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* INTEGRATOR_CONSERVE_VIRTUAL_SPACE */
    {
    V3_BASE,		/* V360EPC register */
    V3_BASE,
    ROUND_UP (V3_REGS_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_PCI */
    {
    INTEGRATOR_MBRD_SSRAM_BASE,
    INTEGRATOR_MBRD_SSRAM_BASE,
    ROUND_UP (INTEGRATOR_MBRD_SSRAM_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    /*
     * The following entry is for the "real" address of the Core Module
     * SDRAM (as opposed to the alias in low memory). The size of the area
     * mapped here is for the amount that has been "occluded" by the Core
     * Module SSRAM from zero upwards.
     */
    {
    INTEGRATOR_HDR0_SDRAM_BASE,
    INTEGRATOR_HDR0_SDRAM_BASE,
    ROUND_UP (INTEGRATOR_HDR_SSRAM_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };
#endif /* defined(CPU_720T/720T_T/920T/920T_T/926E/1020E/1022E/1136JF) */
#if defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)

/*
 * The following structure describes the various different regions of the
 * memory map to be used only during initialization by
 * vmMpuGlobalMapInit() when INCLUDE_MMU_MPU is defined.
 *
 * On the MPUs, the virtual and physical addresses must be
 * the same.  In addition, the regions must have an alignment equal to
 * their size, with a minimum size of 4K.  This restriction is very
 * important in understanding the region definitions.  Regions cannot be
 * arbitrarily moved or their size changed without considering
 * alignment.  There is no page-table RAM overhead to mapping in large
 * areas of the memory map, but we can only define 8 memory regions in
 * total. Regions cannot be marked as read-only in VxWorks.
 *
 * Here, we (arbitrarily) choose to leave as many regions in the MPU
 * unused as possible, so that they are available for later use (e.g. to
 * mark areas of RAM as non-cacheable).  This means that large areas are
 * mapped in as valid where no memory or I/O devices are actually
 * present.  If this is not desired, larger numbers of smaller regions
 * could be defined which more closely match what is actually present in
 * the memory map (paying close attention to the alignment requirements
 * mentioned above).  Spurious accesses outside those defined regions
 * would then cause access violation exceptions when the MPU is switched
 * on.
 *
 * Note that potentially important areas of memory space are currently
 * unmapped.  Core module alias areas, and the EBI space
 * (Boot ROM and SSRAM) are not defined, and will therefore cause
 * access violations.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    /*
     * Map the peripheral register area as writable but not cached or
     * buffered.
     */
    {
    INTEGRATOR_PERIPHERAL_BASE,	/* virtual address */
    INTEGRATOR_PERIPHERAL_BASE,	/* physical address */

    /* Region must have alignment equal to size, minimum of PAGE_SIZE */

    ROUND_UP(INTEGRATOR_PERIPHERAL_SIZE, PAGE_SIZE),	/* length */

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*
     * Main RAM region from 0 to max(SSRAM,SDRAM), marked cacheable and
     * bufferable. Must always be the second entry.
     */

    {
    0,	/* virtual address */
    0,	/* physical address */

    /* Region must have alignment equal to size, minimum of PAGE_SIZE */

    ROUND_UP ((LOCAL_MEM_SIZE + LOCAL_MEM_LOCAL_ADRS), PAGE_SIZE), /* length */

    /* initial state: */

    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE
                        | VM_STATE_MASK_BUFFERABLE) ,

    VM_STATE_VALID	| VM_STATE_WRITABLE
    /* 940 errata "do not use write-back memory regions" */
#if defined(CPU_940T)  || defined(CPU_940T_T)
    | VM_STATE_CACHEABLE_WRITETHROUGH
#else
    | VM_STATE_CACHEABLE | VM_STATE_BUFFERABLE
#endif

    },

#if (LOCAL_MEM_LOCAL_ADRS != 0)

    /*
     * If (e.g. on 946ES) we have image starting above where the