integrator.h

workbench下vxworks6.6的ARM920T核对应的BSP源码

#define V3_LB_SIZE                      0x00000068
#define V3_LB_IO_BASE                   0x0000006E
#define V3_FIFO_CFG                     0x00000070
#define V3_FIFO_PRIORITY                0x00000072
#define V3_FIFO_STAT                    0x00000074
#define V3_LB_ISTAT                     0x00000076
#define V3_LB_IMASK                     0x00000077
#define V3_SYSTEM                       0x00000078
#define V3_LB_CFG                       0x0000007A
#define V3_PCI_CFG                      0x0000007C
#define V3_DMA_PCI_ADR0                 0x00000080
#define V3_DMA_PCI_ADR1                 0x00000090
#define V3_DMA_LOCAL_ADR0               0x00000084
#define V3_DMA_LOCAL_ADR1               0x00000094
#define V3_DMA_LENGTH0                  0x00000088
#define V3_DMA_LENGTH1                  0x00000098
#define V3_DMA_CSR0                     0x0000008B
#define V3_DMA_CSR1                     0x0000009B
#define V3_DMA_CTLB_ADR0                0x0000008C
#define V3_DMA_CTLB_ADR1                0x0000009C
#define V3_DMA_DELAY                    0x000000E0
#define V3_MAIL_DATA                    0x000000C0
#define V3_PCI_MAIL_IEWR                0x000000D0
#define V3_PCI_MAIL_IERD                0x000000D2
#define V3_LB_MAIL_IEWR                 0x000000D4
#define V3_LB_MAIL_IERD                 0x000000D6
#define V3_MAIL_WR_STAT                 0x000000D8
#define V3_MAIL_RD_STAT                 0x000000DA
#define V3_QBA_MAP                      0x000000DC

/* SYSTEM register bits */

#define V3_SYSTEM_M_RST_OUT             BIT15
#define V3_SYSTEM_M_LOCK                BIT14

/*  PCI_CFG bits */

#define V3_PCI_CFG_M_RETRY_EN           BIT10
#define V3_PCI_CFG_M_AD_LOW1            BIT9
#define V3_PCI_CFG_M_AD_LOW0            BIT8

/* PCI MAP register bits (PCI -> Local bus) */

#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH        BIT15
#define V3_PCI_MAP_M_ROM_SIZE           BIT11+BIT10
#define V3_PCI_MAP_M_SWAP               BIT9+BIT8
#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
#define V3_PCI_MAP_M_REG_EN             BIT1
#define V3_PCI_MAP_M_ENABLE             BIT0

/* 9 => 512M window size */

#define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090

/* A => 1024M window size */

#define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0

/* LB_BASE register bits (Local bus -> PCI) */

#define V3_LB_BASE_M_MAP_ADR            0xFFF00000
#define V3_LB_BASE_M_SWAP               BIT9+BIT8
#define V3_LB_BASE_M_ADR_SIZE           0x000000F0
#define V3_LB_BASE_M_PREFETCH           BIT3
#define V3_LB_BASE_M_ENABLE             BIT0

/* LB_MAP register bits (Local bus -> PCI) */

#define V3_LB_MAP_M_MAP_ADR             0xFFF0
#define V3_LB_MAP_M_TYPE                0x000E
#define V3_LB_MAP_M_AD_LOW_EN           BIT0

/* PCI COMMAND REGISTER bits */

#define V3_COMMAND_M_FBB_EN             BIT9
#define V3_COMMAND_M_SERR_EN            BIT8
#define V3_COMMAND_M_PAR_EN             BIT6
#define V3_COMMAND_M_MASTER_EN          BIT2
#define V3_COMMAND_M_MEM_EN             BIT1
#define V3_COMMAND_M_IO_EN              BIT0

/* size of area defined in memory map for V3 registers */

#define V3_REGS_SIZE			0x10000


/* defines for generic pciIoMapLib.c code */

#define PCI_IN_BYTE(x)		*(volatile UINT8 *) (x)
#define PCI_OUT_BYTE(x,y)	*(volatile UINT8 *) (x) = (UINT8)  y
#define PCI_IN_WORD(x)		*(volatile UINT16 *)(x)
#define PCI_OUT_WORD(x,y)	*(volatile UINT16 *)(x) = (UINT16) y
#define PCI_IN_LONG(x)		*(volatile UINT32 *)(x)
#define PCI_OUT_LONG(x,y)	*(volatile UINT32 *)(x) = (UINT32) y

/* restrict use to the first bus, by default */

#define PCI_MAX_BUS 1

/* memory map as seen by the CPU on the local bus */

#define CPU_PCI_IO_ADRS		0x60000000 	/* PCI I/O space base */
#define CPU_PCI_IO_SIZE		0x10000

#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
#define CPU_PCI_CNFG_SIZE	0x1000000

#define CPU_PCI_MEM_ADRS	0x40000000
#define CPU_PCI_MEM_SIZE	0x10000000

/* PCI view of PCI space for PCI devices */

#define PCI_IO_ADRS             0x00000000      /* base of PCI I/O address */
#define PCI2DRAM_BASE_ADRS      0x80000000      /* memory seen from PCI bus */

/* PCI view of PCI memory space for PCI memory devices */

#define PCI_MEM_ADRS		0x40000000	/* base of PCI memory space */

/* PCI address to CPU address offset */

#define PCI2CPU_IO_OFFSET	(CPU_PCI_IO_ADRS - PCI_IO_ADRS)
#define PCI2CPU_MEM_OFFSET	(CPU_PCI_MEM_ADRS - PCI_MEM_ADRS)

/* PCI bus resources */

#define PCI_IO_SIZE		0x00004000	/* PCI I/O slot size */
#define PCI_MEM_SIZE		0x00004000	/* PCI memory slot size */

#define PCI_MEM_ADR0            PCI_MEM_ADRS
#define PCI_IO_ADR0             PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0            PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0            INT_LVL_PCI_0	/* Interrupt level */
#define PCI_INT_VEC0            INT_VEC_PCI_0	/* Interrupt vector */

#define PCI_MEM_ADR1            PCI_MEM_ADR0 + PCI_MEM_SIZE
#define PCI_IO_ADR1             PCI_IO_ADR0 + PCI_IO_SIZE
#define PCI_IO_SIZE1            PCI_IO_SIZE
#define PCI_INT_LVL1            INT_LVL_PCI_1
#define PCI_INT_VEC1            INT_VEC_PCI_1

#define PCI_MEM_ADR2            PCI_MEM_ADR1 + PCI_MEM_SIZE
#define PCI_IO_ADR2             PCI_IO_ADR1 + PCI_IO_SIZE
#define PCI_IO_SIZE2            PCI_IO_SIZE
#define PCI_INT_LVL2            INT_LVL_PCI_2
#define PCI_INT_VEC2            INT_VEC_PCI_2


/* PCI memory base address register configuration mode */

#define FORCE		0x00	/* overwrite membase address register */
#define AUTO		0x01	/* read membase address register */

/*
 * Need to use automatic configuration mode using the resource assigning in
 * pciAssignResources().
 */

#define PCI_REG_MOD	AUTO	/* define the register configuration mode */

#define TYPE_ALLOC	1000

/*
 * Definitions for Ethernet driver buffer use.
 *
 * The buffers to be shared across the PCI bus in must not have addresses
 * in low memory which refer to header card SSRAM (which is not
 * reachable from the PCI bus). We can do several things:
 *
 * 1. Simply allow the driver to use use cacheDmaMalloc() without
 * checking the addresses returned. Because of where the heap usually
 * is, cacheDmaMalloc() in default kernels will generally return
 * addresses which are "low-aliases" for SDRAM and not header card SSRAM.
 * To use this option, do not define INTEGRATOR_ENET_FIXED_BUF_ADRS and do
 * not define the parameter INTEGRATOR_ENET_CHECK_BUFFERS. Header cards for
 * later CPUs may have more local SSRAM, so this may become more of a problem
 * with those later cards.
 *
 * 2. Use cacheDmaMalloc() in the BSP initialisation code, but check that the
 * memory returned is not, in fact, SSRAM, but is actually SDRAM. To use this
 * option define the parameter INTEGRATOR_ENET_CHECK_BUFFERS. A disadvantage
 * of this is that the BSP then needs knowledge of the relationship between
 * buffer space required and the numbers of transmit and receive buffers to be
 * allocated, which would normally be kept within the driver. This is the
 * option configured by default.
 *
 * 3. Define the buffer address to be a specific address, which is
 * accessible from the PCI bus.
 * (a) One possibility is the unaliased SDRAM at its real (high) address.
 * To use this option, define INTEGRATOR_ENET_FIXED_BUF_ADRS and define
 * INTEGRATOR_XXX_BUF_ADRS to be INTEGRATOR_SDRAM_ALIAS_BASE.
 * All of the SDRAM is mapped at the high address, but the size of the
 * part that is not aliased down to low memory, will be the size of the
 * header card SSRAM. On 720T, there is 256 Kbytes and on 920T, we have 1
 * megabyte.
 * (b) Another possibility is the motherboard SSRAM, though early
 * motherboards have a fault that prevents this SSRAM from being accessed
 * from PCI unless the FPGAs on the board have been upgraded. To use this
 * option, define INTEGRATOR_ENET_FIXED_BUF_ADRS and define
 * INTEGRATOR_ENET_XXX_BUF_ADRS to be INTEGRATOR_MBRD_SSRAM_ALIAS_BASE
 * (+ offset if required).
 *
 * In the FEI driver, we use ((nCFDs + 5*nRFDs) * 1544) + 4 bytes.
 * On 720T, this is more than the size of the unaliased SDRAM (256 kbytes),
 * so if we use that area, we need to adjust the number of CFDs and
 * RFDs downwards slightly.
 *
 * Note that all of the fixed address options listed above will suffer a
 * performance penalty over using low-aliased-SDRAM.
 *
 * 4. Reserve an area of SDRAM (at the low alias, but above the end of
 * header card SSRAM) to use for the buffer memory.
 *
 * The drivers will check that the amount of memory given is sufficient
 * for the numbers of CFDs and RFDs and will fail to load if there is a
 * mismatch.
 *
 * Obviously, if only one of the FEI and DEC drivers is being used, then buffer
 * space need only be allocated for the one being used.
 */

#undef  INTEGRATOR_ENET_FIXED_BUF_ADRS	/* do not use fixed address bufs */
#undef INTEGRATOR_ENET_CHECK_BUFFERS	/* check cacheDmaMalloc() addresses */


#ifdef  INTEGRATOR_ENET_FIXED_BUF_ADRS

/*
 * Provide definitions for the buffer address for the three possible PCI cards.
 * The SDRAM alias address should be available on all boards.
 */

#define INTEGRATOR_ENET_PRIMARY_BUF_ADRS INTEGRATOR_SDRAM_ALIAS_BASE

/* next two areas require a later board, or the FPGAs to have been upgraded */

#define INTEGRATOR_ENET_SECONDARY_BUF_ADRS INTEGRATOR_MBRD_SSRAM_BASE
#define INTEGRATOR_ENET_TERTIARY_BUF_ADRS (INTEGRATOR_MBRD_SSRAM_BASE + 0x40000)
#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */


#define INTEGRATOR_DEC_BUF_SIZE	0x30000

/*
 * Assuming we are on a 720T, and three drivers are being started, the
 * smallest slot is 256 kbytes, so reduce memory usage to fit into 256 Kbyte
 * slot. This can be overridden, if we know differently.
 */

#if defined (INTEGRATOR_ENET_FIXED_BUF_ADRS)
#define INTEGRATOR_FEI_BUF_SIZE	0x40000
#define INTEGRATOR_FEI_NUM_CFDS	28
#define INTEGRATOR_FEI_NUM_RFDS	28
#else
#define INTEGRATOR_FEI_BUF_SIZE	0x49000
#define INTEGRATOR_FEI_NUM_CFDS	32
#define INTEGRATOR_FEI_NUM_RFDS	32
#endif


/*
 * Max number of END devices we support - we currently set to three for
 * three PCI slots.
 */

#define INTEGRATOR_MAX_END_DEVS 3

/*
 * Max number of VGA devices we support - we currently set to three for
 * three PCI slots.
 */

#define INTEGRATOR_MAX_VGA_DEVS 3


/* Definitions for LED controller and sysLedsReadWrite */

#define LED_BASE        0x1A000000
#define LED_ALPHA 	(LED_BASE + 0x00)
#define LED_LIGHTS	(LED_BASE + 0x04)
#define LED_SWITCHES	(LED_BASE + 0x08)

#define LED_STATUS	0x01

#define LED_0		0x01
#define LED_1		0x02
#define LED_2		0x04
#define LED_4		0x08

#define LED_LEDS_MASK	0x0F


#define ARM966_I_SRAM_ENABLE    (1<<12)
#define ARM966_WBUFF_ENABLE     (1<<3)
#define ARM966_D_SRAM_ENABLE    (1<<2)

/* definition for power management instrumentation */
#ifdef POWER_MGT_INSTRUMENT
#define SYS_CLK_INT_ENABLE_ENTRY_INDICATOR     UINT16 leds; \
    AMBA_TIMER_READ(LED_LIGHTS,leds); \
    leds = leds ^ LED_1; \
    AMBA_TIMER_WRITE(LED_LIGHTS, leds);

#define SYS_ONE_SHOT_ENABLE_ENTRY_INDICATOR     UINT16 leds; \
    AMBA_TIMER_READ(LED_LIGHTS,leds); \
    leds = leds | LED_0; \
    AMBA_TIMER_WRITE(LED_LIGHTS, leds);
#define SYS_ONE_SHOT_DISABLE_EXIT_INDICATOR
    AMBA_TIMER_READ(LED_LIGHTS,leds); \
    leds = leds & ~LED_0; \
    AMBA_TIMER_WRITE(LED_LIGHTS, leds);
#endif

#ifndef _ASMLANGUAGE
#ifdef INCLUDE_POWER_MGMT_CPU_BSP_SUPPORT
IMPORT void sysCpuPwrEnable (void);
#endif


#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif	/* INCintegratorh */