📄 integrator.h
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#define INTEGRATOR_SC_ID_OFFSET (0x00)#define INTEGRATOR_SC_OSC_OFFSET (0x04)#define INTEGRATOR_SC_CTRLS_OFFSET (0x08)#define INTEGRATOR_SC_CTRLC_OFFSET (0x0C)#define INTEGRATOR_SC_DEC_OFFSET (0x10)#define INTEGRATOR_SC_ARB_OFFSET (0x14)#define INTEGRATOR_SC_PCIENABLE_OFFSET (0x18)#define INTEGRATOR_SC_LOCK_OFFSET (0x1C)#define INTEGRATOR_SC_BASE (0x11000000)#define INTEGRATOR_SC_ID \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)#define INTEGRATOR_SC_OSC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)#define INTEGRATOR_SC_CTRLS \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)#define INTEGRATOR_SC_CTRLC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)#define INTEGRATOR_SC_DEC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)#define INTEGRATOR_SC_ARB \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)#define INTEGRATOR_SC_PCIENABLE \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)#define INTEGRATOR_SC_LOCK \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)#define INTEGRATOR_SC_OSC_SYS_10MHz (0x20)#define INTEGRATOR_SC_OSC_SYS_15MHz (0x34)#define INTEGRATOR_SC_OSC_SYS_20MHz (0x48)#define INTEGRATOR_SC_OSC_SYS_25MHz (0x5C)#define INTEGRATOR_SC_OSC_SYS_33MHz (0x7C)#define INTEGRATOR_SC_OSC_SYS_MASK (0xFF)#define INTEGRATOR_SC_OSC_PCI_25MHz (0x100)#define INTEGRATOR_SC_OSC_PCI_33MHz (0x0)#define INTEGRATOR_SC_OSC_PCI_MASK (0x100)#define FL_SC_CONTROL 0x06 /* Enable Flash Write and Vpp *//* - Hard coded id of the core module we are compiling for. */#define CORE_MODULE 0/* * interrupt control stuff * Note: FIQ is not handled within VxWorks so this is just IRQ */#define IC_BASE (0x14000000 + (CORE_MODULE * 0x40))#define IRQ_STATUS (IC_BASE+0x000) /* Read */#define IRQ_RAW_STATUS (IC_BASE+0x004) /* Read */#define IRQ_ENABLE (IC_BASE+0x008) /* Read/Write */#define IRQ_DISABLE (IC_BASE+0x00C) /* Write */#define IRQ_SOFT (IC_BASE+0x010) /* Read/Write */#define IRQ_SOFTCLR (IC_BASE+0x014) /* Write */#define FIQ_STATUS (IC_BASE+0x020) /* Read */#define FIQ_RAW_STATUS (IC_BASE+0x024) /* Read */#define FIQ_ENABLE (IC_BASE+0x028) /* Read/Write */#define FIQ_DISABLE (IC_BASE+0x02C) /* Write */#define AMBA_INT_NUM_LEVELS 22#define AMBA_INT_CSR_PEND IRQ_STATUS#define AMBA_INT_CSR_ENB IRQ_ENABLE#define AMBA_INT_CSR_DIS IRQ_DISABLE#define AMBA_INT_CSR_MASK 0x003FFFFF /* Mask out invalid status bits *//* Interrupt levels */#define INT_LVL_SOFT 0 /* soft interrupt */#define INT_LVL_UART_0 1 /* UART 0 */#define INT_LVL_UART_1 2 /* UART 1 */#define INT_LVL_KEYBOARD 3 /* keyboard interrupt */#define INT_LVL_MOUSE 4 /* mouse interrupt */#define INT_LVL_TIMER_0 5 /* timer 0 */#define INT_LVL_TIMER_1 6 /* timer 1 */#define INT_LVL_TIMER_2 7 /* timer 2 */#define INT_LVL_RTC 8 /* real-time clock */#define INT_LVL_EXP0 9 /* logic module 0 */#define INT_LVL_EXP1 10 /* logic module 1 */#define INT_LVL_EXP2 11 /* logic module 2 */#define INT_LVL_EXP3 12 /* logic module 3 */#define INT_LVL_PCI_0 13 /* PCI int A */#define INT_LVL_PCI_1 14 /* PCI int B */#define INT_LVL_PCI_2 15 /* PCI int C */#define INT_LVL_PCI_3 16 /* PCI int D */#define INT_LVL_PCIBRIDGE 17 /* V3 PCI bridge interrupt */#define INT_LVL_DEG 18 /* CompactPCI aux (DEG#) */#define INT_LVL_ENUM 19 /* CompactPCI aux (ENUM#) */#define INT_LVL_PCILB 20 /* PCI local bus fault */#define INT_LVL_APC 21 /* AutoPC external int *//* interrupt vectors */#define INT_VEC_SOFT IVEC_TO_INUM(INT_LVL_SOFT)#define INT_VEC_UART_0 IVEC_TO_INUM(INT_LVL_UART_0)#define INT_VEC_UART_1 IVEC_TO_INUM(INT_LVL_UART_1)#define INT_VEC_KEYBOARD IVEC_TO_INUM(INT_LVL_KEYBOARD)#define INT_VEC_MOUSE IVEC_TO_INUM(INT_LVL_MOUSE)#define INT_VEC_TIMER_0 IVEC_TO_INUM(INT_LVL_TIMER_0)#define INT_VEC_TIMER_1 IVEC_TO_INUM(INT_LVL_TIMER_1)#define INT_VEC_TIMER_2 IVEC_TO_INUM(INT_LVL_TIMER_2)#define INT_VEC_RTC IVEC_TO_INUM(INT_LVL_RTC)#define INT_VEC_EXP0 IVEC_TO_INUM(INT_LVL_EXP0)#define INT_VEC_EXP1 IVEC_TO_INUM(INT_LVL_EXP1)#define INT_VEC_EXP2 IVEC_TO_INUM(INT_LVL_EXP2)#define INT_VEC_EXP3 IVEC_TO_INUM(INT_LVL_EXP3)#define INT_VEC_PCI_0 IVEC_TO_INUM(INT_LVL_PCI_0)#define INT_VEC_PCI_1 IVEC_TO_INUM(INT_LVL_PCI_1)#define INT_VEC_PCI_2 IVEC_TO_INUM(INT_LVL_PCI_2)#define INT_VEC_PCI_3 IVEC_TO_INUM(INT_LVL_PCI_3)#define INT_VEC_PCIBRIDGE IVEC_TO_INUM(INT_LVL_PCIBRIDGE)#define INT_VEC_DEG IVEC_TO_INUM(INT_LVL_DEG)#define INT_VEC_ENUM IVEC_TO_INUM(INT_LVL_ENUM)#define INT_VEC_PCILB IVEC_TO_INUM(INT_LVL_PCILB)#define INT_VEC_APC IVEC_TO_INUM(INT_LVL_APC)/* definitions for the AMBA UART */#define UART_XTAL_FREQ INTEGRATOR_UARTCLK /* UART baud rate clk freq */#define N_SIO_CHANNELS N_AMBA_UART_CHANNELS#define N_UART_CHANNELS N_AMBA_UART_CHANNELS#define N_AMBA_UART_CHANNELS 2 /* number of AMBA UART chans */#define UART_0_BASE_ADR 0x16000000 /* UART 0 base address */#define UART_1_BASE_ADR 0x17000000 /* UART 1 base address *//* definitions for the keyboard */#define KBD_BASE_ADR 0x18000000 /* Keyboard 0 base address */#define MOUSE_BASE_ADR 0x19000000 /* Mouse 1 base address */#define KBD_REGS_SIZE 0x14#define MOUSE_REGS_SIZE 0x14/* definitions for the AMBA Timer */#define AMBA_TIMER_BASE 0x13000000 /* Address of base of timer */#define AMBA_BASE_OFFSET 0X100#define AMBA_TIMER0_BASE ((AMBA_TIMER_BASE))#define AMBA_TIMER1_BASE ((AMBA_TIMER_BASE) + AMBA_BASE_OFFSET)#define AMBA_TIMER2_BASE ((AMBA_TIMER_BASE) + 2 * AMBA_BASE_OFFSET)#define SYS_TIMER_BASE AMBA_TIMER1_BASE#define AUX_TIMER_BASE AMBA_TIMER0_BASE#define SLEEP_TIMER_BASE AMBA_TIMER2_BASE#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_1)#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_0)#define SLEEP_TIMER_INT_LVL (INT_LVL_TIMER_2)/* Add corresponding INT_VEC definitions for intConnect calls. */#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_1)#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_0)#define AMBA_TIMER_SYS_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)#define AMBA_TIMER_SYS_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)#define AMBA_TIMER_AUX_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)#define AMBA_TIMER_AUX_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)/* Frequency of counter/timers */#define SYS_TIMER_CLK (INTEGRATOR_CLK24MHZ/16)#define AUX_TIMER_CLK (INTEGRATOR_SYSCLK/16)#define SLEEP_TIMER_CLK (INTEGRATOR_CLK24MHZ/16)#define AMBA_RELOAD_TICKS 0 /* No overhead *//* Mask out unused bits from timer register. */#define AMBA_TIMER_VALUE_MASK 0xFFFF/** Note: the numbering below is 1,2,3 instead of 0,1,2.* This matches the definitions in ambaTimer.h*//* Sys Clk is timer 2 */#define SYS_TIMER_CLEAR AMBA_TIMER_T2CLEAR#define SYS_TIMER_CTRL AMBA_TIMER_T2CTRL#define SYS_TIMER_LOAD AMBA_TIMER_T2LOAD#define SYS_TIMER_VALUE AMBA_TIMER_T2VALUE/* Aux Clk is timer 1 */#define AUX_TIMER_CLEAR AMBA_TIMER_T1CLEAR#define AUX_TIMER_CTRL AMBA_TIMER_T1CTRL#define AUX_TIMER_LOAD AMBA_TIMER_T1LOAD#define AUX_TIMER_VALUE AMBA_TIMER_T1VALUE/* Sleep Clk is timer 3 */#define SLEEP_TIMER_CLEAR AMBA_TIMER_T3CLEAR#define SLEEP_TIMER_CTRL AMBA_TIMER_T3CTRL#define SLEEP_TIMER_LOAD AMBA_TIMER_T3LOAD#define SLEEP_TIMER_VALUE AMBA_TIMER_T3VALUE/* * Clock rates depend upon CPU power and work load of application. * The values below are minimum and maximum allowed by the hardware. * So: * min frequency = roundup(clock_rate/(max_counter_value)) * max frequency = rounddown(clock_rate/(min_counter_value)) * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK * AUX_CLK_RATE_MAX = AUX_TIMER_CLK * * However, we must set maxima that are sustainable on a running * system determined by experimentation. * * The following values have been determined by experimentation. */#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)#if defined(CPU_920T) || defined(CPU_920T_T)#define SYS_CLK_RATE_MAX 25000#elif defined(CPU_926E) || defined(CPU_926E_T)#define SYS_CLK_RATE_MAX 25000#elif defined(CPU_1136JF)#define SYS_CLK_RATE_MAX 5000#else#define SYS_CLK_RATE_MAX 4000#endif#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)#if defined(CPU_920T) || defined(CPU_920T_T)#define AUX_CLK_RATE_MAX 25000#elif defined(CPU_926E) || defined(CPU_926E_T)#define AUX_CLK_RATE_MAX 25000#elif defined(CPU_1136JF)#define AUX_CLK_RATE_MAX 7000#else#define AUX_CLK_RATE_MAX 6000#endif/* PCI definitions *//* Interrupt number for PCI */#define INT_NUM_IRQ0 INT_LVL_PCI_0/* V3 PCI bridge controller */#define V3_BASE 0x62000000 /* V360EPC registers *//* Bit field definitions */#define BIT0 0x00000001#define BIT1 0x00000002#define BIT2 0x00000004#define BIT3 0x00000008#define BIT4 0x00000010#define BIT5 0x00000020#define BIT6 0x00000040#define BIT7 0x00000080#define BIT8 0x00000100#define BIT9 0x00000200#define BIT10 0x00000400#define BIT11 0x00000800#define BIT12 0x00001000#define BIT13 0x00002000#define BIT14 0x00004000#define BIT15 0x00008000#define BIT16 0x00010000#define BIT17 0x00020000#define BIT18 0x00040000#define BIT19 0x00080000#define BIT20 0x00100000/* Handy sizes */#define SZ_1K 0x00000400#define SZ_4K 0x00001000#define SZ_8K 0x00002000#define SZ_16K 0x00004000#define SZ_64K 0x00010000#define SZ_128K 0x00020000#define SZ_256K 0x00040000#define SZ_512K 0x00080000#define SZ_1M 0x00100000#define SZ_2M 0x00200000#define SZ_4M 0x00400000#define SZ_8M 0x00800000#define SZ_16M 0x01000000#define SZ_32M 0x02000000#define SZ_64M 0x04000000#define SZ_128M 0x08000000#define SZ_256M 0x10000000#define SZ_512M 0x20000000#define SZ_1G 0x40000000#define SZ_2G 0x80000000/* V3 Local Bus to PCI Bridge definitions */#define V3_PCI_VENDOR 0x00000000#define V3_PCI_DEVICE 0x00000002#define V3_PCI_CMD 0x00000004#define V3_PCI_STAT 0x00000006#define V3_PCI_CC_REV 0x00000008#define V3_PCI_HDR_CFG 0x0000000C#define V3_PCI_IO_BASE 0x00000010#define V3_PCI_BASE0 0x00000014#define V3_PCI_BASE1 0x00000018#define V3_PCI_SUB_VENDOR 0x0000002C#define V3_PCI_SUB_ID 0x0000002E#define V3_PCI_ROM 0x00000030#define V3_PCI_BPARAM 0x0000003C#define V3_PCI_MAP0 0x00000040#define V3_PCI_MAP1 0x00000044#define V3_PCI_INT_STAT 0x00000048#define V3_PCI_INT_CFG 0x0000004C#define V3_LB_BASE0 0x00000054#define V3_LB_BASE1 0x00000058#define V3_LB_MAP0 0x0000005E#define V3_LB_MAP1 0x00000062#define V3_LB_BASE2 0x00000064#define V3_LB_MAP2 0x00000066⌨️ 快捷键说明
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