sysalib.s

workbench下vxworks6.6的ARM920T核对应的BSP源码

/* sysALib.s - ARM Integrator system-dependent routines */

/*
 * Copyright (c) 1999-2001, 2003-2007 Wind River Systems, Inc.
 *
 * The right to copy, distribute or otherwise make use of this software
 * may be licensed only pursuant to the terms of an applicable Wind River
 * license agreement.
 */

/*
modification history
--------------------
01t,16oct07,j_b  adjustment for >16-bit MMU_INIT_VALUE for 926e (WIND00060071)
01s,26sep07,mdo  Clear out apigen errors/warnings
01r,04jan06,jb  Fix incomplete comment bug
01q,22sep05,h_k  fixed undef symbol sysIntStackSplit. (SPR #112718)
01p,20jul05,h_k  corrected _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK conditions.
01o,11jul05,h_k  cleaned up interrupt stack protection decoupling.
01n,01apr05,rec  fix typo in CPU_926E preprocessor statements
01m,29mar05,jb   Adding 1136jf support
01l,09feb05,rec  fix boot type
01k,04nov04,rec  add power management support for 926 and 946
01j,12aug04,scm  add 926E support...
01i,29may03,rec  Power Management
01i,04feb03,jb   Adding ARM10 Support
01h,09oct01,jpd  added clock speed setting for 946ES.
01g,03oct01,jpd  tidied slightly.
01f,28sep01,pr   added support for ARM946E.
01g,04jun01,rec  memory clock rate changes for 740t
01f,21feb01,h_k  added support for ARM966ES and ARM966ES_T.
01e,23oct00,jpd  changed speeds on 920T; added conditional early
		 enabling of instruction cache on 920T.
01d,21feb00,jpd  added further initialisation code.
01c,07feb00,jpd  added support for ARM720T and ARM920T.
01b,13jan00,pr	 added support for ARM740T.
01a,15nov99,ajb  copied from pid940t version 01h.
*/

/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.  It contains the entry code, sysInit(), for VxWorks images
that start running from RAM, such as 'vxWorks'.  These images are
loaded into memory by some external program (e.g., a boot ROM) and then
started.  The routine sysInit() must come first in the text segment.
Its job is to perform the minimal setup needed to call the generic C
routine usrInit().

sysInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer.  Other hardware and
device initialization is performed later in the sysHwInit routine in
sysLib.c.

NOTE
The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

INCLUDE FILES:

SEE ALSO:
\tb "ARM Architecture Reference Manual,"
\tb "ARM 7TDMI Data Sheet,"
\tb "ARM 720T Data Sheet,"
\tb "ARM 740T Data Sheet,"
\tb "ARM 920T Technical Reference Manual",
\tb "ARM 940T Technical Reference Manual",
\tb "ARM 946E-S Technical Reference Manual",
\tb "ARM 966E-S Technical Reference Manual",
\tb "ARM 1020E Technical Reference Manual",
\tb "ARM 1022E Technical Reference Manual",
\tb "ARM 1136JF-S Technical Reference Manual",
\tb "ARM Reference Peripherals Specification,"
\tb "ARM Integrator/AP User Guide",
\tb "ARM Integrator/CM7TDMI User Guide",
\tb "ARM Integrator/CM720T User Guide",
\tb "ARM Integrator/CM740T User Guide",
\tb "ARM Integrator/CM920T User Guide",
\tb "ARM Integrator/CM926EJ-S User Guide",
\tb "ARM Integrator/CM940T User Guide",
\tb "ARM Integrator/CM946E User Guide",
\tb "ARM Integrator/CM9x6ES Datasheet".
\tb "ARM Integrator/CM10200 User Guide",
\tb "ARM Integrator/CM1136JF-S User Guide",
*/


#define _ASMLANGUAGE
#include <vxWorks.h>
#include <asm.h>
#include <regs.h>
#include <sysLib.h>
#include "config.h"
#include <arch/arm/mmuArmLib.h>

/* internals */
	.globl  FUNC(sysInit)           /* start of system code */
#ifndef	_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
	.globl  FUNC(sysIntStackSplit)  /* routine to split interrupt stack */
#endif	/* !_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */

#if defined(CPU_966ES) || defined(CPU_966ES_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T)  || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1136JF)
	.globl  FUNC(archPwrDown)       /* power down callback */
#endif

/* externals */

	.extern	FUNC(usrInit)		/* system initialization routine */

#ifndef	_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
	.extern	FUNC(vxSvcIntStackBase) /* base of SVC-mode interrupt stack */
	.extern	FUNC(vxSvcIntStackEnd)	/* end of SVC-mode interrupt stack */
	.extern	FUNC(vxIrqIntStackBase) /* base of IRQ-mode interrupt stack */
	.extern	FUNC(vxIrqIntStackEnd)	/* end of IRQ-mode interrupt stack */
#endif	/* !_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_740T) || defined(CPU_740T_T)

/* variables */

	.data
	.balign	1			/* no alignment necessary */

	/* variable used with a SWPB instruction to drain the write-buffer */

sysCacheSwapVar:
	.byte	0
	.balign	4

#endif /* defined(720T/720T_T/740T/740T_T) */

	.text
	.balign 4

/*******************************************************************************
*
* sysInit - start after boot
*
* This routine is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.
*
* SYNOPSIS
* \ss
* sysInit
*     (
*     int startType     /@ THIS IS NOT A CALLABLE ROUTINE @/
*     )
* \se
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A
*
* sysInit ()              /@ THIS IS NOT A CALLABLE ROUTINE @/
*
*/

_ARM_FUNCTION(sysInit)

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)

	/*
	 * Set processor and MMU to known state as follows (we may have not
	 * been entered from a reset). We must do this before setting the CPU
	 * mode as we must set PROG32/DATA32.
	 *
	 * MMU Control Register layout.
	 *
	 * bit
	 *  0 M 0 MMU disabled
	 *  1 A 0 Address alignment fault disabled, initially
	 *  2 C 0 Data cache disabled
	 *  3 W 0 Write Buffer disabled
	 *  4 P 1 PROG32
	 *  5 D 1 DATA32
	 *  6 L 1 Should Be One (Late abort on earlier CPUs)
	 *  7 B ? Endianness (1 => big)
	 *  8 S 0 System bit to zero } Modifies MMU protections, not really
	 *  9 R 1 ROM bit to one     } relevant until MMU switched on later.
	 * 10 F 0 Should Be Zero
	 * 11 Z 0 Should Be Zero (Branch prediction control on 810)
	 * 12 I 0 Instruction cache control
	 */

	/* Setup MMU Control Register */

	LDR	r1, =MMU_INIT_VALUE		/* Defined in mmuArmLib.h */


	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */
#if defined(CPU_1020E)
        NOP
        NOP
        NOP
#endif /* defined(CPU_1020E) */

	/*
	 * If MMU was on before this, then we'd better hope it was set
	 * up for flat translation or there will be problems. The next
	 * 2/3 instructions will be fetched "translated" (number depends
	 * on CPU).
	 *
	 * We would like to discard the contents of the Write-Buffer
	 * altogether, but there is no facility to do this. Failing that,
	 * we do not want any pending writes to happen at a later stage,
	 * so drain the Write-Buffer, i.e. force any pending writes to
	 * happen now.
	 */

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_740T) || defined(CPU_740T_T)
	LDR	r2, L$_sysCacheSwapVar	/* R2 -> sysCacheSwapVar */
	SWPB	r1, r1, [r2]

	/* Flush, (i.e. invalidate) all entries in the ID-cache */

	MCR	CP_MMU, 0, r1, c7, c0, 0	/* Flush (inval) all ID-cache */
#endif /* defined(CPU_720T,740T) */

#if defined(CPU_920T)  || defined(CPU_920T_T)  || \
    defined(CPU_926E) || defined(CPU_926E_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)
	MOV	r1, #0				/* data SBZ */
	MCR	CP_MMU, 0, r1, c7, c10, 4	/* drain write-buffer */
#if defined(CPU_1020E)
        NOP
        NOP
        NOP
#endif /* defined(CPU_1020E) */

	/* Flush (invalidate) both I and D caches */

	MCR	CP_MMU, 0, r1, c7, c7, 0	/* R1 = 0 from above, data SBZ*/
#if defined(CPU_1020E)
        NOP
        NOP
        NOP
#endif /* defined(CPU_1020E) */

#if defined (CPU_926E) || defined (CPU_926E_T)
        LDR     r1, L$_sysCacheUncachedAdrs     /* R2 -> uncached area */
        LDR     r1, [r1]                        /* synchronize L2 AHB */
#endif /* defined (CPU_926E,926E_T) */

#if defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_926E) || defined(CPU_926E_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)
#if defined(INTEGRATOR_EARLY_I_CACHE_ENABLE)
	MRC	CP_MMU, 0, r1, c1, c0, 0
        ORR     r1, r1, #MMUCR_I_ENABLE         /* conditionally enable Icache*/
	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */
#endif /* defined(INTEGRATOR_EARLY_I_CACHE_ENABLE) */
#endif /* defined(CPU_920T/920T_T/926E/1020E/1022E/1136) */

#endif /* defined(CPU_920T,926E, 946ES,1020E,1022E, 1136JF) */

#if defined(CPU_940T) || defined(CPU_940T_T)
	LDR	r1, L$_sysCacheUncachedAdrs	/* R1 -> uncached area */
	LDR	r1, [r1]			/* drain write-buffer */

	/* Flush (invalidate) both caches */

	MOV	r1, #0				/* data SBZ */
	MCR	CP_MMU, 0, r1, c7, c5, 0	/* Flush (inval) all I-cache */
	MCR	CP_MMU, 0, r1, c7, c6, 0	/* Flush (inval) all D-cache */
#endif /* defined(940T,940T_T) */

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)  || \
    defined(CPU_1136JF)
        /*
         * Set Process ID Register to zero, this effectively disables
         * the process ID remapping feature.
         */

        MOV     r1, #0
        MCR     CP_MMU, 0, r1, c13, c0, 0
#if defined(CPU_1020E)
        NOP
        NOP
        NOP
#endif /* defined(CPU_1020E) */
#endif /* defined(CPU_720T,920T,926E,1020E, 1022E) */

#if defined (CPU_926E) || defined (CPU_926E_T) || \
    defined (CPU_946ES) || defined (CPU_946ES_T) || \
    defined (CPU_1020E) || defined (CPU_1020E_T) || \
    defined (CPU_1136JF)

        /* Set Context ID Register to zero, including Address Space ID */

        MCR     CP_MMU, 0, r1, c13, c0, 1
#endif /* defined (CPU_926E, 946ES) */

#endif /* defined(CPU_720T,740T,920T,926E,940T,946ES,1020E,1022E) */

	/* disable interrupts in CPU and switch to SVC32 mode */

	MRS	r1, cpsr
	BIC	r1, r1, #MASK_MODE
	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT
	MSR	cpsr, r1

	/*
	 * CPU INTERRUPTS DISABLED
	 *
	 * disable individual interrupts in the interrupt controller
	 */

	MOV	r2, #IC_BASE			/* R2->interrupt controller */
	MVN	r1, #0				/* &FFFFFFFF */
	STR	r1, [r2, #FIQ_DISABLE-IC_BASE]	/* disable all FIQ sources */
	STR	r1, [r2, #IRQ_DISABLE-IC_BASE]	/* disable all IRQ sources */


#if !defined (CPU_1136JF)

	/* Setup asynchronous clocking (eg. core and memory clocks different) */

	LDR	r1, =INTEGRATOR_HDR_BASE
	LDR	r2, [r1, #INTEGRATOR_HDR_OSC_OFFSET]
	AND	r2, r2, #(3 << 23)
	CMP	r2, #(1 << 23)
	BNE	clock1

#if defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_940T) || defined(CPU_940T_T)
	/*
	 * if HDR_OSC indicates (bits[23:24] = 01), set
	 * implementation-specific bits in the MMU control register - set
	 * asynchronous mode.
	 */

	MRC	CP_MMU, 0, r2, c1, c0, 0
	ORR	r2, r2, #MMUCR_ASYNC
	MCR	CP_MMU, 0, r2, c1, c0, 0
#endif

clock1:
	/* If bits[23:24] were 0, set asynchronous mode in HDR_CTRL */

	LDRLT	r2, [r1, #INTEGRATOR_HDR_CTRL_OFFSET]
	BICLT	r2, r2, #INTEGRATOR_HDR_CTRL_FASTBUS