config.h

workbench下vxworks6.6的ARM920T核对应的BSP源码

 */

#define INTEGRATOR_DELAY_VALUE	0x1000

/*
 * Flash/NVRAM memory configuration
 *
 * A block of the Flash memory (FLASH_SIZE bytes at FLASH_ADRS) is
 * reserved for non-volatile storage of data.
 *
 * See also integrator.h
 */

#define INCLUDE_FLASH

#ifdef INCLUDE_FLASH
#define FLASH_SIZE		0x00020000	/* one 128kbyte block of Flash*/
#define NV_RAM_SIZE		0x100		/* how much we use as NVRAM */
#undef	NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		0		/* bootline at start of NVRAM */
#undef FLASH_NO_OVERLAY				/* read-modify-write can be done for
									 * all of Flash */
#define INCLUDE_FLASH_SIB_FOOTER		/* add a SIB footer to block */
#else	/* INCLUDE_FLASH */
#define NV_RAM_SIZE		NONE

#endif	/* INCLUDE_FLASH */

/* Serial port configuration */

#undef	NUM_TTY
#define NUM_TTY			N_SIO_CHANNELS

#define DEFAULT_BAUD      9600

/*
 * Define SERIAL_DEBUG to enable debugging
 * via the serial ports
 */
#undef SERIAL_DEBUG

/* INCLUDE_WDB is defined by default in configAll.h.
 * INCLUDE_BOOT_WDB can be defined to add WDB support to the bootroms.
 */
#if defined(INCLUDE_WDB) || defined (INCLUDE_BOOT_WDB)
      #undef WDB_COMM_TYPE
      #undef WDB_TTY_BAUD
      #undef WDB_TTY_CHANNEL
      #undef WDB_TTY_DEV_NAME

     #ifdef SERIAL_DEBUG
      #define WDB_NO_BAUD_AUTO_CONFIG
      #define WDB_COMM_TYPE       WDB_COMM_SERIAL /* WDB in Serial mode */
      #define WDB_TTY_BAUD        115200        /* Baud rate for WDB Connection */
      #define WDB_TTY_CHANNEL     1           /* COM PORT #2 */
      #define WDB_TTY_DEV_NAME    "/tyCo/1"   /* default TYCODRV_5_2 device name */
     #else /* SERIAL_DEBUG */
      #define WDB_COMM_TYPE       WDB_COMM_END
      #define WDB_TTY_BAUD        DEFAULT_BAUD    /* Baud rate for WDB Connection */
      #define WDB_TTY_CHANNEL     0               /* COM PORT #1 */
      #define WDB_TTY_DEV_NAME    "/tyCo/0"       /* default TYCODRV_5_2 device name */
     #endif /* SERIAL_DEBUG */
#endif /* INCLUDE_WDB || INCLUDE_BOOT_WDB */

/*
 * Cache/MMU configuration
 *
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)  || \
    defined(CPU_1136JF)

/*
 * We use the generic architecture libraries, with caches/MMUs present. A
 * call to sysHwInit0() is needed from within usrInit before
 * cacheLibInit() is called.
 */

#ifndef _ASMLANGUAGE
IMPORT void sysHwInit0 (void);
#endif
#define INCLUDE_SYS_HW_INIT_0
#define SYS_HW_INIT_0()         sysHwInit0 ()

#endif /* defined(720T/740T/920T/926E/940T/946ES/1020E/1022E/1136JF) */

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_740T) || defined(CPU_740T_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)
/*
 * These processors can be either write-through or copyback (defines whether
 * write-buffer is enabled); cache itself is write-through.
 */

#undef  USER_I_CACHE_MODE
#define USER_I_CACHE_MODE	CACHE_COPYBACK

/*
 * 720T and 740T have a combined Instruction/Data cache, so the modes must
 * be identical.
 */

#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE	(USER_I_CACHE_MODE)

#endif /* defined(720T/720T_T/740T/740T_T/CPU_1020E/CPU_1022E/CPU_1136JF) */

#if defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_926E)  || defined(CPU_926E_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)
/*
 * 920T/926E/940T/946ES I-cache mode is a bit of an inappropriate concept,
 * but use this.
 * */

#undef  USER_I_CACHE_MODE
#define USER_I_CACHE_MODE       CACHE_WRITETHROUGH

/* 920T/926E/940T/946ES has to be this. */

#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE       CACHE_COPYBACK

#endif /* defined(CPU_920T/926E/940T/946ES) */

#if defined(CPU_940T) || defined(CPU_940T_T) || \
    defined(CPU_926E) || defined(CPU_926E_T)

/*
 * All ARM 940T and 926ES BSPs must define a variable sysCacheUncachedAdrs: a
 * pointer to a word that is uncached and is safe to read (i.e. has no
 * side effects).  This is used by the cacheLib code to perform a read
 * (only) to drain the write-buffer. Clearly this address must be present
 * within one of the regions created within sysPhysMemDesc, where it must
 * be marked as non-cacheable. There are many such addresses we could use
 * on the board, but we choose to use an address here that will be
 * mapped in on just about all configurations: a safe address within the
 * interrupt controller: the IRQ Enabled status register. This saves us
 * from having to define a region just for this pointer. This constant
 * defined here is used to initialise sysCacheUncachedAdrs in sysLib.c
 * and is also used by the startup code in sysALib.s and romInit.s in
 * draining the write-buffer.
 */

#define SYS_CACHE_UNCACHED_ADRS               AMBA_INT_CSR_ENB
#endif /* defined(CPU_940T/940T_T) */

#if defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)

/*
 * 740T/940T/946E have an MPU and not a full MMU, so only INCLUDE_MMU_MPU can be
 * supported, and not full page-table-style MMU. Include support for
 * the MPU by default (this can be overridden, if desired).
 */

#undef	INCLUDE_MMU_BASIC
#define INCLUDE_MMU_MPU

#endif /* defined(740T/940T/946ES) */


#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_926E) || defined(CPU_926E_T) || \
    defined(CPU_1020E) || defined(CPU_1022E) || \
    defined(CPU_1136JF)

/*
 * Include MMU BASIC and CACHE support for command line and project builds
 */
#define	INCLUDE_MMU_BASIC
#define INCLUDE_BOOT_MMU_BASIC
#define INCLUDE_CACHE_SUPPORT

#endif /* defined(720T/720T_T/920T/920T_T/926E/CPU_1020E/CPU_1022E/CPU_1136JF) */

#if defined(CPU_1136JF)

/*
 * Vector Floating Point Support
 */

#define INCLUDE_VFP

#endif /* defined(CPU_1136JF) */

/*
 * Network driver configuration.
 *
 * De-select unused (default) network drivers selected in configAll.h.
 */

#undef	INCLUDE_ENP		/* include CMC Ethernet interface*/
#undef	INCLUDE_EX		/* include Excelan Ethernet interface */
#undef	INCLUDE_SM_NET		/* include backplane net interface */
#undef	INCLUDE_SM_SEQ_ADDR	/* shared memory network auto address setup */

/* Enhanced Network Driver (END) Support */

#define INCLUDE_END

#ifdef	INCLUDE_END
#define INCLUDE_DEC21X40END	/* include PCI-based DEC 21X4X END Ethernet */
#define INCLUDE_FEI82557END	/* include PCI-based Intel END Ethernet */

#ifndef SERIAL_DEBUG
#define WBD_AGENT_END
#else
#undef WBD_AGENT_END
#endif /* SERIAL_DEBUG */

#ifdef INCLUDE_DEC21X40END
#define INCLUDE_MIILIB
#endif

#endif  /* INCLUDE_END */


/* PCI configuration */

#define INCLUDE_PCI


/*
 * Interrupt mode - interrupts can be in either preemptive or non-preemptive
 * mode.  For non-preemptive mode, change INT_MODE to INT_NON_PREEMPT_MODEL
 */

#define INT_MODE	INT_PREEMPT_MODEL

/*
 * Enable BSP-configurable interrupt priorities: order of servicing and
 * masking of interrupts will be determined by ambaIntLvlPriMap[] in
 * sysLib.c.  If AMBA_INT_PRIORITY_MAP is not defined, priority of
 * interrupts will be least-significant bit first.
 */

#define	AMBA_INT_PRIORITY_MAP	/* BSP-configurable interrupt priorities */


/*
 * miscellaneous definitions
 * Note: ISR_STACK_SIZE is defined here rather than in ../all/configAll.h
 * (as is more usual) because the stack size depends on the interrupt
 * structure of the BSP.
 */

#define ISR_STACK_SIZE	0x2000	/* size of ISR stack, in bytes */


/* Optional timestamp support */

#undef	INCLUDE_TIMESTAMP	/* define to include timestamp driver */
#define INCLUDE_TIMESTAMP


/* Optional TrueFFS support */

#undef	INCLUDE_TFFS		/* define to include TrueFFS driver */

#ifdef INCLUDE_TFFS
#define INCLUDE_SHOW_ROUTINES
#endif /* INCLUDE_TFFS */

/* ------- new features independent of layer ------- */

#define INCLUDE_SIO_POLL
#define SIO_POLL_CONSOLE	0	/* 0 = PrimeCell UART1
					 * 1 = PrimeCell UART2
					 */

#include "integrator.h"

#undef INCLUDE_WINDML          /* define to include windML support */

/*
 * For vxWorks 6.xx, ARM boot offsets moved out of page 0 in order
 * to support kernel hardening (vector page protection)...
 *
 * This BSP by default enables vxWorks 5.xx bootrom compatibility which
 * does not support kernel hardening.
 *
 * If INCLUDE_KERNEL_HARDENING is defined, 6.xx bootroms will need to
 * be flashed.
 */

/* undefine the following symbol if using 6.xx bootroms */
#undef T2_BOOTROM_COMPATIBILITY

#if (!defined (INCLUDE_KERNEL_HARDENING) && defined (T2_BOOTROM_COMPATIBILITY))
   #undef SM_ANCHOR_OFFSET
   #define SM_ANCHOR_OFFSET        0x600
   #undef BOOT_LINE_OFFSET
   #define BOOT_LINE_OFFSET        0x700
   #undef EXC_MSG_OFFSET
   #define EXC_MSG_OFFSET          0x800
#endif /* !defined (INCLUDE_KERNEL_HARDENING) && defined (T2_BOOTROM_COMPATIBILITY) */

#if (defined (INCLUDE_KERNEL_HARDENING) && defined (T2_BOOTROM_COMPATIBILITY))
   #warning "T2_BOOTROM_COMPATIBILITY enabled with INCLUDE_KERNEL_HARDENING check config.h!"
   #warning "Current configuration is not compatible with vxWorks 5.xx bootroms!"
#endif

#ifdef __cplusplus
}
#endif
#endif  /* INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif