config.h

workbench下vxworks6.6的ARM920T核对应的BSP源码

/* config.h - ARM Integrator configuration header */

/*
 * Copyright (c) 1999-2007 Wind River Systems, Inc.
 *
 * The right to copy, distribute or otherwise make use of this software
 * may be licensed only pursuant to the terms of an applicable Wind River
 * license agreement.
 */

/*
modification history
--------------------
02v,04jun07,d_l  Undefine FLASH_NO_OVERLAY macro.(WIND00062985) 
02u,20mar07,rec  enable MMU in bootrom
02t,22feb07,jmt  Defect 88186 - remove INCLUDE_WDB from config.h
02s,18jan07,j_b  remove excess components
02r,01dec06,j_b  Added support for the IPNet Network Stack
02q,11mar06,jb   Fix for SPRs 118173 and 118369 - T2_BOOTROM_COMPATIBILITY
02p,07mar06,jmt  Define SYS_MODEL to define sysModel string
02o,25jan06,jb   Adding VFP Support for 1136
02n,13dec05,jb   920t is re-enabled. Change entry point to allow for kernel
                 hardening
02m,24aug05,h_k  cleaned up VXLAYER.
02l,15aug05,h_k  undef INCLUDE_MMU_BASIC and define INCLUDE_MMU_GLOBAL_MAP for
                 lower layers.
02k,08aug05,h_k  fixed buffer overflow at sioPollInput in USER_APPL_INIT.
                 added or excluded some components in various layers.
02j,14jul05,h_k  changed MK_ALLOC to MEM_ALLOT. enabled MMU and cache in MKL by
                 default.
02i,08jul05,h_k  removed INCLUDE_SERIAL. added VXLAYER.
02h,16may05,scm  spr 108763 -Base 6 ARM offsets moved out of page 0
02g,13apr05,jb   Bumping BSP Rev
02f,11apr05,jb   Remove Test configuration
02e,29mar05,jb   Adding 1136JF support
02d,09mar05,rec  SPR-106845 add T2 bootrom backward compatibility
02c,14jun05,pcm  removed INCLUDE_DOSFS
02b,07mar05,rec  fix LOCAL_MEM_SIZE typo for 926
02a,28feb05,rec  change RAM_LOW_ADRS
01z,07dec04,rec  update for base6
01y,12aug04,scm  add 926E support...
01x,29may03,rec  Power Management, increase ISR_STACK_SIZE
01w,07feb03,jb   Removing unwanted define
01v,04feb03,jb   Adding ARM10 support
01u,15jul02,m_h  WindML support, C++ protection
01t,22may02,m_h  Reduce ROM_SIZE for boards with 32 meg RAM (77901)
01s,15may02,m_h  INCLUDE_SHELL, etc are for BSP validation (75760, 75904)
01r,09oct01,jpd  corrected RAM_HIGH_ADRS and LOCAL_MEM_SIZE for integrator946.
                 bump revision number to /5
01q,03oct01,jpd  added support for Integrator 946es/946es_t.
01p,02may01,rec  bump revision number, fix 559 initialization problem
01o,01nov01,t_m  merge in 946 updates
01n,22oct01,jb   Setting MMU_BASIC as default for builds of cpus with MMU
01m,15oct01,jb   New assembly macros are in h/arch/arm/arm.h
01l,09oct01,jpd  corrected RAM_HIGH_ADRS and LOCAL_MEM_SIZE for integrator946.
01k,03oct01,jpd  added support for Integrator 946es/946es_t.
01j,02may01,rec  bump revision number, fix 559 initialization problem
01i,27apr01,rec  add support for 966
01h,25jan01,jmb  remove INCLUDE_MIILIB
01g,15dec00,rec  change RAM_HIGH_ADRS
01f,21nov00,jpd  added support for Intel Ethernet driver.
01e,17feb00,jpd  added define of INCLUDE_FLASH_SIB_FOOTER; raised RAM_HIGH_ADRS.
01d,07feb00,jpd  added support for ARM720T and ARM920T.
01c,13jan00,pr	 add support for Integrator 740T/740T_T.
01b,07dec99,pr	 add DEC and PCI support.
01a,05nov99,ajb  copied from PID BSP version 01p.
*/

/*
This module contains the configuration parameters for the ARM Integrator BSP.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
extern "C" {
#endif

/* BSP version/revision identification, before configAll.h */

#define BSP_VER_1_1     1       /* 1.2 is backwards compatible with 1.1 */
#define BSP_VER_1_2     1
#define BSP_VERSION	"2.0"
#define BSP_REV		"/13"	/* 0 for first revision */

#include <configAll.h>

/*
 * STANDALONE_NET must be defined for network debug with
 * standalone vxWorks
 */

#define STANDALONE_NET

/* SYS_MODEL define
*
* NOTE
* This define does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
*/
#if	defined(CPU_7TDMI)
    #define SYS_MODEL "ARM Integrator - ARM7TDMI (ARM)"
#elif	defined(CPU_7TDMI_T)
    #define SYS_MODEL "ARM Integrator - ARM7TDMI (Thumb)"
#elif	defined(CPU_720T)
    #define SYS_MODEL "ARM Integrator - ARM720T (ARM)"
#elif	defined(CPU_720T_T)
    #define SYS_MODEL "ARM Integrator - ARM720T (Thumb)"
#elif	defined(CPU_740T)
    #define SYS_MODEL "ARM Integrator - ARM740T (ARM)"
#elif	defined(CPU_740T_T)
    #define SYS_MODEL "ARM Integrator - ARM740T (Thumb)"
#elif	defined(CPU_920T)
    #define SYS_MODEL "ARM Integrator - ARM920T (ARM)"
#elif	defined(CPU_926E)
    #define SYS_MODEL "ARM Integrator - ARM926E (ARM)"
#elif   defined(CPU_926E_T)
    #define SYS_MODEL "ARM Integrator - ARM926E (Thumb)"
#elif	defined(CPU_920T_T)
    #define SYS_MODEL "ARM Integrator - ARM920T (Thumb)"
#elif	defined(CPU_940T)
    #define SYS_MODEL "ARM Integrator - ARM940T (ARM)"
#elif	defined(CPU_940T_T)
    #define SYS_MODEL "ARM Integrator - ARM940T (Thumb)"
#elif   defined(CPU_946ES)
    #define SYS_MODEL "ARM Integrator - ARM946ES (ARM)"
#elif   defined(CPU_946ES_T)
    #define SYS_MODEL "ARM Integrator - ARM946ES (Thumb)"
#elif   defined(CPU_966ES)
    #define SYS_MODEL "ARM Integrator - ARM966ES (ARM)"
#elif   defined(CPU_966ES_T)
    #define SYS_MODEL "ARM Integrator - ARM966ES (Thumb)"
#elif   defined(CPU_1020E)
    #define SYS_MODEL "ARM Integrator - ARM1020E (ARM)"
#elif   defined(CPU_1022E)
    #define SYS_MODEL "ARM Integrator - ARM1022E (ARM)"
#elif   defined(CPU_1136JF)
    #define SYS_MODEL "ARM Integrator - ARM1136JF (ARM)"
#else
#error CPU not supported
#endif	/* defined(CPU_7TDMI) */

/*
 * Support network devices.
 */

#define  INCLUDE_NETWORK

#if	defined(CPU_7TDMI)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator7t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_7TDMI_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator7t_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_720T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator720t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_720T_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator720t_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_740T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator740t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_740T_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator740t_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_920T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator920t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_926E)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator926ejs/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_926E_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator926ejs_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_920T_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator920t_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_940T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator940t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_940T_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator940t_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_966ES)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator966es/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_966ES_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator966es_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_946ES)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator946es/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_946ES_T)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator946es_t/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_1020E)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator10200/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_1022E)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator10220/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#elif defined(CPU_1136JF)
#  define DEFAULT_BOOT_LINE \
    "fei(0,0) host:/tor2/target/config/integrator1136jfs/vxWorks " \
    "h=90.0.0.3 e=90.0.0.50:ffffff00 u=target tn=targetname"
#else
#  error CPU type not supported
#endif  /* defined(CPU_7TDMI) */

/* Memory configuration */

#undef	LOCAL_MEM_AUTOSIZE			/* run-time memory sizing */
#define USER_RESERVED_MEM	0		/* see sysMemTop() */

/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#if defined(CPU_946ES) || defined(CPU_946ES_T)
#define LOCAL_MEM_LOCAL_ADRS	0x00100000	/* fixed at 1Mbyte after TCM */
#define LOCAL_MEM_BUS_ADRS	0x00100000	/* fixed at 1Mbyte after TCM */
#define LOCAL_MEM_SIZE		0x00700000	/* 7 Mbytes after TCM */
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#  define LOCAL_MEM_LOCAL_ADRS	0x08000000	/* fixed at 0x08000000 */
#  define LOCAL_MEM_BUS_ADRS	0x08000000	/* fixed at 0x08000000 */
#define LOCAL_MEM_SIZE		0x00800000	/* 8 Mbytes */
#elif defined(CPU_1020E) || defined(CPU_1022E)
#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at 2Mbyte after TCM */
#define LOCAL_MEM_BUS_ADRS	0x00000000	/* fixed at 2Mbyte after TCM */
#define LOCAL_MEM_SIZE		0x01000000 + INTEGRATOR_HDR_SSRAM_SIZE	/* 16 Mbytes after TCM */
#define INTEGRATOR_EARLY_I_CACHE_ENABLE		/* Enable Early I-Cache */
#define INTEGRATOR_CONSERVE_VIRTUAL_SPACE	/* The speeds up boot significantly */
#define LOCAL_MEM_AUTOSIZE			/* Enable AUTOSIZE */
#elif defined(CPU_926E) || defined(CPU_926E_T) || defined(CPU_1136JF)
#define INTEGRATOR_EARLY_I_CACHE_ENABLE         /* Enable Early I-Cache */
#define INTEGRATOR_CONSERVE_VIRTUAL_SPACE       /* The speeds up boot significantly */
#define LOCAL_MEM_LOCAL_ADRS    0x00000000
#define LOCAL_MEM_BUS_ADRS      0x00000000
#define LOCAL_MEM_SIZE          0x08000000
#define LOCAL_MEM_AUTOSIZE                      /* Enable AUTOSIZE */
#elif defined(CPU_920T)
#  define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */
#  define LOCAL_MEM_BUS_ADRS	0x00000000	/* fixed at zero */
#define LOCAL_MEM_SIZE		0x02000000	/* 32 Mbytes */
#else
#  define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */
#  define LOCAL_MEM_BUS_ADRS	0x00000000	/* fixed at zero */
#define LOCAL_MEM_SIZE		0x00800000	/* 8 Mbytes */
#endif
#define LOCAL_MEM_END_ADRS	(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE)

/*
 * Boot ROM is an image written into Flash. Part of the Flash can be
 * reserved for boot parameters etc. (see the Flash section below).
 *
 * The following parameters are defined here and in the Makefile.
 * They must be kept synchronized; effectively config.h depends on Makefile.
 * Any changes made here must be made in the Makefile and vice versa.
 *
 * ROM_BASE_ADRS is the base of the Flash ROM/EPROM.
 * ROM_TEXT_ADRS is the entry point of the VxWorks image
 * ROM_SIZE is the size of the part of the Flash ROM/EPROM allocated to
 *		the VxWorks image (block size - size of headers)
 *
 * Two other constants are used:
 * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
 * 		 (e.g. in uncompressed boot ROM)
 * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
 *
 * The values are given as literals here to make it easier to ensure
 * that they are the same as those in the Makefile.
 */

#define ROM_BASE_ADRS       0x24000000     /* base of Flash/EPROM */
#define ROM_TEXT_ADRS       ROM_BASE_ADRS  /* code start addr in ROM */
#define ROM_SIZE            0x00100000     /* size of ROM holding VxWorks*/

#define ROM_COPY_SIZE       ROM_SIZE
#define ROM_SIZE_TOTAL      0x02000000	/* total size of ROM */

#if defined(CPU_946ES) || defined(CPU_946ES_T)
#  define RAM_LOW_ADRS		0x00101000	/* VxWorks image entry point */
#  define RAM_HIGH_ADRS		0x00600000	/* RAM address for ROM boot */
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#  define RAM_LOW_ADRS		0x08001000	/* VxWorks image entry point */
#  define RAM_HIGH_ADRS		0x08600000	/* RAM address for ROM boot */
#elif defined(CPU_1020E) || defined(CPU_1022E)
#  define RAM_LOW_ADRS		0x00201000	/* VxWorks image entry point */
#  define RAM_HIGH_ADRS		0x00600000	/* RAM address for ROM boot */
#elif defined(CPU_1136JF) || defined(CPU_920T) || defined(CPU_926E)
#  define RAM_LOW_ADRS		0x00004000	/* VxWorks image entry point */
#  define RAM_HIGH_ADRS		0x00600000	/* RAM address for ROM boot */
#else
#  define RAM_LOW_ADRS		0x00002000	/* VxWorks image entry point */
#  define RAM_HIGH_ADRS		0x00600000	/* RAM address for ROM boot */
#endif

/*
 * Count for a CPU delay loop at the beginning of romInit. There have been
 * reports of problems with certain boards and certain power supplies, and
 * adding a delay at the start of romInit appears to help with this. This
 * value may need tuning for different board/PSU combinations.