📄 hardware.lst
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00008387 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008388 40 92 R1 = 0x0000 // 24MHz Fosc
00008389 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
0000838B 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000838C 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000838E 09 93 ED FC R1 = 0xfced // 15.625K
00008390 19 D3 0A 70 [P_TimerA_Data]=R1
00008392 09 93 A8 00 R1 = 0x00A8 //
00008394 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
00008396 09 93 FF FF R1 = 0xffff
00008398 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000839A 11 93 01 00 R1 = [R_InterruptStatus] //
0000839C 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
0000839E 19 D3 01 00 [R_InterruptStatus] = R1 //
000083A0 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083A2 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
000083A3 60 92 R1=0x0020;
000083A4 19 D3 13 70 [P_SystemClock]=R1
000083A6 09 93 A8 00 R1 = 0x00A8; //
000083A8 19 D3 2A 70 [P_DAC_Ctrl]= R1
000083AA 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083AB 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
000083AD 09 93 00 FE R1 = 0xfe00; // 24K
000083AF 19 D3 0A 70 [P_TimerA_Data] = R1;
000083B1 09 93 FF FF R1 = 0xffff
000083B3 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000083B5 11 93 01 00 R1 = [R_InterruptStatus] //
000083B7 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000083B9 19 D3 01 00 [R_InterruptStatus] = R1 //
000083BB 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083BD 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
000083BE 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
000083BF 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
000083C1 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083C2 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
000083C4 40 92 R1 = 0x0000 // Fosc/2
000083C5 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
000083C7 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
000083C9 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
000083CB 09 93 FF FF R1 = 0xffff
000083CD 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000083CF 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
000083D0 46 92 R1 = 0x0006
000083D1 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083D3 09 93 00 FE R1 = 0xFE00
000083D5 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083D7 11 93 01 00 R1 = [R_InterruptStatus] //
000083D9 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
000083DB 19 D3 01 00 [R_InterruptStatus] = R1 //
000083DD 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083DF 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
000083E0 09 93 A8 00 R1 = 0x00A8
000083E2 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083E4 09 93 00 FE R1 = 0xFE00
000083E6 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083E8 11 93 01 00 R1 = [R_InterruptStatus] //
000083EA 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083EC 19 D3 01 00 [R_InterruptStatus] = R1 //
000083EE 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083F0 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
000083F1 09 93 A8 00 R1 = 0x00A8
000083F3 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083F5 09 93 9A FD R1 = 0xFD9A
000083F7 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083F9 11 93 01 00 R1 = [R_InterruptStatus] //
000083FB 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083FD 19 D3 01 00 [R_InterruptStatus] = R1 //
000083FF 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008401 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
00008402 09 93 A8 00 R1 = 0x00A8
00008404 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008406 09 93 00 FD R1 = 0xFD00
00008408 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000840A 11 93 01 00 R1 = [R_InterruptStatus] //
0000840C 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000840E 19 D3 01 00 [R_InterruptStatus] = R1 //
00008410 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008412 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
00008413 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00008414 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
00008416 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008417 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00008419 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
0000841B 19 D3 0A 70 [P_TimerA_Data] = r1;
0000841D 75 92 r1 = 0x0035; // ADINI should be open (107)
0000841E 19 D3 15 70 [P_ADC_Ctrl] = r1;
00008420 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
00008422 19 D3 2A 70 [P_DAC_Ctrl] = r1;
00008424 09 93 FF FF r1 = 0xffff;
00008426 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
00008428 11 93 01 00 R1 = [R_InterruptStatus] //
0000842A 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000842C 19 D3 01 00 [R_InterruptStatus] = R1 //
0000842E 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008430 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
00008431 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
00008432 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
00008434 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
00008436 19 D3 0A 70 [P_TimerA_Data] = r1
00008438 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
00008439 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
0000843A 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
0000843C 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
0000843E 19 D3 0A 70 [P_TimerA_Data] = r1;
00008440 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
00008441 90 D4 push r1,r2 to [sp]
00008442 11 93 17 70 r1=[P_DAC1]
00008444 09 B3 C0 FF r1 &= ~0x003f
00008446 09 43 00 80 cmp r1,0x8000
00008448 0E 0E jb L_RU_NormalUp
00008449 19 5E je L_RU_End
L_RU_DownLoop:
0000844A 40 F0 AD 84 call F_Delay
0000844C 41 94 r2 = 0x0001
0000844D 1A D5 12 70 [P_Watchdog_Clear] = r2
0000844F 09 23 40 00 r1 -= 0x40
00008451 19 D3 17 70 [P_DAC1] = r1
00008453 09 43 00 80 cmp r1,0x8000
00008455 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
00008456 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
00008457 40 F0 AD 84 call F_Delay
00008459 41 94 r2 = 0x0001
0000845A 1A D5 12 70 [P_Watchdog_Clear] = r2
0000845C 09 03 40 00 r1 += 0x40
0000845E 19 D3 17 70 [P_DAC1] = r1
00008460 09 43 00 80 cmp r1, 0x8000
00008462 4C 4E jne L_RU_Loop
L_RU_End:
00008463 90 90 pop r1,r2 from [sp]
00008464 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
00008465 90 D4 push r1,r2 to [sp]
//int off
00008466 11 93 17 70 r1 = [P_DAC1]
00008468 09 B3 C0 FF r1 &= ~0x003F
0000846A 0A 5E jz L_RD_End
L_RD_Loop:
0000846B 40 F0 AD 84 call F_Delay
0000846D 41 94 r2 = 0x0001
0000846E 1A D5 12 70 [P_Watchdog_Clear] = r2
00008470 09 23 40 00 r1 -= 0x40
00008472 19 D3 17 70 [P_DAC1] = r1
00008474 4A 4E jnz L_RD_Loop
L_RD_End:
//int fiq,irq
00008475 90 90 pop r1,r2 from [sp]
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