📄 hardware.lst
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// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
00000001 .IRAM
00000001 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.define C_RampDelayTime 16
.define C_QueueSize 100
00000002 00 00 .VAR R_Queue
00000003 00 00 00 00 .DW C_QueueSize-1 DUP(0)
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00000066 00 00 .VAR R_ReadIndex
00000067 00 00 .VAR R_WriteIndex
0000831B .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
0000831B 09 93 02 00 R1 = R_Queue
0000831D 40 94 R2 = 0
L_ClearQueueLoop?:
0000831E D1 D4 [R1++] = R2
0000831F 09 43 66 00 cmp R1, R_Queue+C_QueueSize
00008321 44 4E jne L_ClearQueueLoop?
00008322 40 92 R1 = 0
00008323 19 D3 66 00 [R_ReadIndex] = R1
00008325 19 D3 67 00 [R_WriteIndex] = R1
00008327 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
00008328 12 95 66 00 R2 = [R_ReadIndex]
0000832A 12 45 67 00 cmp R2,[R_WriteIndex]
0000832C 0D 5E je L_RQ_QueueEmpty
0000832D 0A 05 02 00 R2 += R_Queue // get queue data address
0000832F C2 92 R1 = [R2]
00008330 12 95 66 00 R2 = [R_ReadIndex]
00008332 41 04 R2 += 1
00008333 0A 45 64 00 cmp R2, C_QueueSize
00008335 01 4E jne L_RQ_NotQueueBottom
00008336 40 94 R2 = 0
L_RQ_NotQueueBottom:
00008337 1A D5 66 00 [R_ReadIndex] = R2
//r2 = 0x0000 // get queue data
00008339 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
0000833A 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
0000833B 12 95 66 00 R2 = [R_ReadIndex]
0000833D 12 45 67 00 cmp R2,[R_WriteIndex]
0000833F 03 5E je L_RQ_QueueEmpty?
00008340 0A 05 02 00 R2 += R_Queue // get queue data index
00008342 C2 92 R1 = [R2]
L_RQ_QueueEmpty?:
00008343 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
00008344 12 95 67 00 R2 = [R_WriteIndex] // put data to queue
00008346 0A 05 02 00 R2 += R_Queue
00008348 C2 D2 [R2] = R1
00008349 12 95 67 00 R2 = [R_WriteIndex]
0000834B 41 04 R2 += 1
0000834C 0A 45 64 00 cmp R2, C_QueueSize
0000834E 01 4E jne L_WQ_NotQueueBottom
0000834F 40 94 R2 = 0
L_WQ_NotQueueBottom:
00008350 1A D5 67 00 [R_WriteIndex] = R2
00008352 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
00008353 11 93 66 00 R1 = [R_ReadIndex]
00008355 11 43 67 00 cmp R1,[R_WriteIndex]
00008357 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
00008358 11 93 66 00 R1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
0000835A 05 4E jnz L_TQ_JudgeCond2
0000835B 11 93 67 00 R1 = [R_WriteIndex]
0000835D 09 43 63 00 cmp R1, C_QueueSize-1 // Cond1
0000835F 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
00008360 11 93 66 00 R1 = [R_ReadIndex]
00008362 41 22 R1 -=1
00008363 11 43 67 00 cmp R1,[R_WriteIndex]
00008365 02 5E je L_TQ_QueueFull
00008366 40 92 r1 = 0 // not Full, not empty
00008367 90 9A retf
L_TQ_QueueFull:
00008368 41 92 r1 = 1 // full
00008369 90 9A retf
L_TQ_QueueEmpty:
0000836A 42 92 r1 = 2 // empty
0000836B 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
// or F_SACM_A2000_Initial:
// Note: The following functions are the partial code of original
// initial subroutine. (H/W setting part)
//
// Ex: F_SACM_A2000_Initial:
// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
0000836C 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
0000836D 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
0000836F 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008370 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
00008372 09 93 00 FD R1 = 0xfd00 // 16K
00008374 19 D3 0A 70 [P_TimerA_Data] = R1
00008376 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
00008378 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000837A 09 93 FF FF R1 = 0xffff
0000837C 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000837E 40 92 R1 =0x0000 //
0000837F 11 93 01 00 R1 = [R_InterruptStatus] //
00008381 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
00008383 19 D3 01 00 [R_InterruptStatus] = R1 //
00008385 19 D3 10 70 [P_INT_Ctrl] = R1 //
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