📄 hardware.lst
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// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
00008364 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
00008365 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
00008367 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008368 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
0000836A 09 93 00 FD R1 = 0xfd00 // 16K
0000836C 19 D3 0A 70 [P_TimerA_Data] = R1
0000836E 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
00008370 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008372 09 93 FF FF R1 = 0xffff
00008374 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008376 40 92 R1 =0x0000 //
00008377 11 93 01 00 R1 = [R_InterruptStatus] //
00008379 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
0000837B 19 D3 01 00 [R_InterruptStatus] = R1 //
0000837D 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000837F 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008380 40 92 R1 = 0x0000 // 24MHz Fosc
00008381 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
00008383 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008384 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
00008386 09 93 ED FC R1 = 0xfced // 15.625K
00008388 19 D3 0A 70 [P_TimerA_Data]=R1
0000838A 09 93 A8 00 R1 = 0x00A8 //
0000838C 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000838E 09 93 FF FF R1 = 0xffff
00008390 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008392 11 93 01 00 R1 = [R_InterruptStatus] //
00008394 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00008396 19 D3 01 00 [R_InterruptStatus] = R1 //
00008398 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000839A 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000839B 60 92 R1=0x0020;
0000839C 19 D3 13 70 [P_SystemClock]=R1
0000839E 09 93 A8 00 R1 = 0x00A8; //
000083A0 19 D3 2A 70 [P_DAC_Ctrl]= R1
000083A2 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083A3 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
000083A5 09 93 00 FE R1 = 0xfe00; // 24K
000083A7 19 D3 0A 70 [P_TimerA_Data] = R1;
000083A9 09 93 FF FF R1 = 0xffff
000083AB 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000083AD 11 93 01 00 R1 = [R_InterruptStatus] //
000083AF 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000083B1 19 D3 01 00 [R_InterruptStatus] = R1 //
000083B3 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083B5 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
000083B6 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
000083B7 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
000083B9 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083BA 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
000083BC 40 92 R1 = 0x0000 // Fosc/2
000083BD 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
000083BF 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
000083C1 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
000083C3 09 93 FF FF R1 = 0xffff
000083C5 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000083C7 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
000083C8 46 92 R1 = 0x0006
000083C9 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083CB 09 93 00 FE R1 = 0xFE00
000083CD 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083CF 11 93 01 00 R1 = [R_InterruptStatus] //
000083D1 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
000083D3 19 D3 01 00 [R_InterruptStatus] = R1 //
000083D5 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083D7 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
000083D8 09 93 A8 00 R1 = 0x00A8
000083DA 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083DC 09 93 00 FE R1 = 0xFE00
000083DE 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083E0 11 93 01 00 R1 = [R_InterruptStatus] //
000083E2 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083E4 19 D3 01 00 [R_InterruptStatus] = R1 //
000083E6 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083E8 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
000083E9 09 93 A8 00 R1 = 0x00A8
000083EB 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083ED 09 93 9A FD R1 = 0xFD9A
000083EF 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083F1 11 93 01 00 R1 = [R_InterruptStatus] //
000083F3 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083F5 19 D3 01 00 [R_InterruptStatus] = R1 //
000083F7 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083F9 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
000083FA 09 93 A8 00 R1 = 0x00A8
000083FC 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083FE 09 93 00 FD R1 = 0xFD00
00008400 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008402 11 93 01 00 R1 = [R_InterruptStatus] //
00008404 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008406 19 D3 01 00 [R_InterruptStatus] = R1 //
00008408 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000840A 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000840B 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000840C 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000840E 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000840F 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00008411 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
00008413 19 D3 0A 70 [P_TimerA_Data] = r1;
00008415 75 92 r1 = 0x0035; // ADINI should be open (107)
00008416 19 D3 15 70 [P_ADC_Ctrl] = r1;
00008418 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000841A 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000841C 09 93 FF FF r1 = 0xffff;
0000841E 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
00008420 11 93 01 00 R1 = [R_InterruptStatus] //
00008422 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
00008424 19 D3 01 00 [R_InterruptStatus] = R1 //
00008426 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008428 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
00008429 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000842A 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000842C 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
0000842E 19 D3 0A 70 [P_TimerA_Data] = r1
00008430 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
00008431 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
00008432 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
00008434 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
00008436 19 D3 0A 70 [P_TimerA_Data] = r1;
00008438 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
00008439 90 D4 push r1,r2 to [sp]
0000843A 11 93 17 70 r1=[P_DAC1]
0000843C 09 B3 C0 FF r1 &= ~0x003f
0000843E 09 43 00 80 cmp r1,0x8000
00008440 0E 0E jb L_RU_NormalUp
00008441 19 5E je L_RU_End
L_RU_DownLoop:
00008442 40 F0 A5 84 call F_Delay
00008444 41 94 r2 = 0x0001
00008445 1A D5 12 70 [P_Watchdog_Clear] = r2
00008447 09 23 40 00 r1 -= 0x40
00008449 19 D3 17 70 [P_DAC1] = r1
0000844B 09 43 00 80 cmp r1,0x8000
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