📄 hardware.lst
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////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
00008315 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
00008316 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
00008318 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008319 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
0000831B 09 93 00 FD R1 = 0xfd00 // 16K
0000831D 19 D3 0A 70 [P_TimerA_Data] = R1
0000831F 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
00008321 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008323 09 93 FF FF R1 = 0xffff
00008325 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008327 40 92 R1 =0x0000 //
00008328 11 93 01 00 R1 = [R_InterruptStatus] //
0000832A 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
0000832C 19 D3 01 00 [R_InterruptStatus] = R1 //
0000832E 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008330 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008331 40 92 R1 = 0x0000 // 24MHz Fosc
00008332 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
00008334 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008335 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
00008337 09 93 ED FC R1 = 0xfced // 15.625K
00008339 19 D3 0A 70 [P_TimerA_Data]=R1
0000833B 09 93 A8 00 R1 = 0x00A8 //
0000833D 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000833F 09 93 FF FF R1 = 0xffff
00008341 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008343 11 93 01 00 R1 = [R_InterruptStatus] //
00008345 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00008347 19 D3 01 00 [R_InterruptStatus] = R1 //
00008349 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000834B 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000834C 60 92 R1=0x0020;
0000834D 19 D3 13 70 [P_SystemClock]=R1
0000834F 09 93 A8 00 R1 = 0x00A8; //
00008351 19 D3 2A 70 [P_DAC_Ctrl]= R1
00008353 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008354 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
00008356 09 93 00 FE R1 = 0xfe00; // 24K
00008358 19 D3 0A 70 [P_TimerA_Data] = R1;
0000835A 09 93 FF FF R1 = 0xffff
0000835C 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000835E 11 93 01 00 R1 = [R_InterruptStatus] //
00008360 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
00008362 19 D3 01 00 [R_InterruptStatus] = R1 //
00008364 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008366 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00008367 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
00008368 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
0000836A 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000836B 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
0000836D 40 92 R1 = 0x0000 // Fosc/2
0000836E 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
00008370 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
00008372 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
00008374 09 93 FF FF R1 = 0xffff
00008376 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008378 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00008379 46 92 R1 = 0x0006
0000837A 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000837C 09 93 00 FE R1 = 0xFE00
0000837E 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008380 11 93 01 00 R1 = [R_InterruptStatus] //
00008382 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00008384 19 D3 01 00 [R_InterruptStatus] = R1 //
00008386 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008388 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00008389 09 93 A8 00 R1 = 0x00A8
0000838B 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000838D 09 93 00 FE R1 = 0xFE00
0000838F 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008391 11 93 01 00 R1 = [R_InterruptStatus] //
00008393 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008395 19 D3 01 00 [R_InterruptStatus] = R1 //
00008397 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008399 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000839A 09 93 A8 00 R1 = 0x00A8
0000839C 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000839E 09 93 9A FD R1 = 0xFD9A
000083A0 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083A2 11 93 01 00 R1 = [R_InterruptStatus] //
000083A4 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083A6 19 D3 01 00 [R_InterruptStatus] = R1 //
000083A8 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083AA 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
000083AB 09 93 A8 00 R1 = 0x00A8
000083AD 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083AF 09 93 00 FD R1 = 0xFD00
000083B1 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083B3 11 93 01 00 R1 = [R_InterruptStatus] //
000083B5 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083B7 19 D3 01 00 [R_InterruptStatus] = R1 //
000083B9 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083BB 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
000083BC 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
000083BD 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
000083BF 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083C0 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
000083C2 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000083C4 19 D3 0A 70 [P_TimerA_Data] = r1;
000083C6 75 92 r1 = 0x0035; // ADINI should be open (107)
000083C7 19 D3 15 70 [P_ADC_Ctrl] = r1;
000083C9 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000083CB 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000083CD 09 93 FF FF r1 = 0xffff;
000083CF 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000083D1 11 93 01 00 R1 = [R_InterruptStatus] //
000083D3 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000083D5 19 D3 01 00 [R_InterruptStatus] = R1 //
000083D7 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083D9 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000083DA 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000083DB 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000083DD 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
000083DF 19 D3 0A 70 [P_TimerA_Data] = r1
000083E1 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000083E2 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000083E3 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000083E5 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000083E7 19 D3 0A 70 [P_TimerA_Data] = r1;
000083E9 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000083EA 90 D4 push r1,r2 to [sp]
000083EB 11 93 17 70 r1=[P_DAC1]
000083ED 09 B3 C0 FF r1 &= ~0x003f
000083EF 09 43 00 80 cmp r1,0x8000
000083F1 0E 0E jb L_RU_NormalUp
000083F2 19 5E je L_RU_End
L_RU_DownLoop:
000083F3 40 F0 56 84 call F_Delay
000083F5 41 94 r2 = 0x0001
000083F6 1A D5 12 70 [P_Watchdog_Clear] = r2
000083F8 09 23 40 00 r1 -= 0x40
000083FA 19 D3 17 70 [P_DAC1] = r1
000083FC 09 43 00 80 cmp r1,0x8000
000083FE 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
000083FF 0C EE jmp L_RU_End
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