📄 hardware.lst
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000082FC 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
000082FD 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
000082FF 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008300 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
00008302 09 93 00 FD R1 = 0xfd00 // 16K
00008304 19 D3 0A 70 [P_TimerA_Data] = R1
00008306 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
00008308 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000830A 09 93 FF FF R1 = 0xffff
0000830C 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000830E 40 92 R1 =0x0000 //
0000830F 11 93 01 00 R1 = [R_InterruptStatus] //
00008311 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
00008313 19 D3 01 00 [R_InterruptStatus] = R1 //
00008315 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008317 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008318 40 92 R1 = 0x0000 // 24MHz Fosc
00008319 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
0000831B 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000831C 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000831E 09 93 ED FC R1 = 0xfced // 15.625K
00008320 19 D3 0A 70 [P_TimerA_Data]=R1
00008322 09 93 A8 00 R1 = 0x00A8 //
00008324 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
00008326 09 93 FF FF R1 = 0xffff
00008328 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000832A 11 93 01 00 R1 = [R_InterruptStatus] //
0000832C 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
0000832E 19 D3 01 00 [R_InterruptStatus] = R1 //
00008330 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008332 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
00008333 60 92 R1=0x0020;
00008334 19 D3 13 70 [P_SystemClock]=R1
00008336 09 93 A8 00 R1 = 0x00A8; //
00008338 19 D3 2A 70 [P_DAC_Ctrl]= R1
0000833A 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000833B 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
0000833D 09 93 00 FE R1 = 0xfe00; // 24K
0000833F 19 D3 0A 70 [P_TimerA_Data] = R1;
00008341 09 93 FF FF R1 = 0xffff
00008343 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008345 11 93 01 00 R1 = [R_InterruptStatus] //
00008347 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
00008349 19 D3 01 00 [R_InterruptStatus] = R1 //
0000834B 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000834D 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000834E 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
0000834F 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
00008351 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008352 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
00008354 40 92 R1 = 0x0000 // Fosc/2
00008355 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
00008357 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
00008359 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
0000835B 09 93 FF FF R1 = 0xffff
0000835D 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000835F 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00008360 46 92 R1 = 0x0006
00008361 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008363 09 93 00 FE R1 = 0xFE00
00008365 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008367 11 93 01 00 R1 = [R_InterruptStatus] //
00008369 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
0000836B 19 D3 01 00 [R_InterruptStatus] = R1 //
0000836D 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000836F 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00008370 09 93 A8 00 R1 = 0x00A8
00008372 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008374 09 93 00 FE R1 = 0xFE00
00008376 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008378 11 93 01 00 R1 = [R_InterruptStatus] //
0000837A 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000837C 19 D3 01 00 [R_InterruptStatus] = R1 //
0000837E 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008380 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
00008381 09 93 A8 00 R1 = 0x00A8
00008383 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008385 09 93 9A FD R1 = 0xFD9A
00008387 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008389 11 93 01 00 R1 = [R_InterruptStatus] //
0000838B 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000838D 19 D3 01 00 [R_InterruptStatus] = R1 //
0000838F 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008391 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
00008392 09 93 A8 00 R1 = 0x00A8
00008394 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008396 09 93 00 FD R1 = 0xFD00
00008398 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000839A 11 93 01 00 R1 = [R_InterruptStatus] //
0000839C 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000839E 19 D3 01 00 [R_InterruptStatus] = R1 //
000083A0 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083A2 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
000083A3 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
000083A4 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
000083A6 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083A7 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
000083A9 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000083AB 19 D3 0A 70 [P_TimerA_Data] = r1;
000083AD 75 92 r1 = 0x0035; // ADINI should be open (107)
000083AE 19 D3 15 70 [P_ADC_Ctrl] = r1;
000083B0 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000083B2 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000083B4 09 93 FF FF r1 = 0xffff;
000083B6 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000083B8 11 93 01 00 R1 = [R_InterruptStatus] //
000083BA 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000083BC 19 D3 01 00 [R_InterruptStatus] = R1 //
000083BE 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083C0 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000083C1 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000083C2 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000083C4 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
000083C6 19 D3 0A 70 [P_TimerA_Data] = r1
000083C8 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000083C9 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000083CA 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000083CC 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000083CE 19 D3 0A 70 [P_TimerA_Data] = r1;
000083D0 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000083D1 90 D4 push r1,r2 to [sp]
000083D2 11 93 17 70 r1=[P_DAC1]
000083D4 09 B3 C0 FF r1 &= ~0x003f
000083D6 09 43 00 80 cmp r1,0x8000
000083D8 0E 0E jb L_RU_NormalUp
000083D9 19 5E je L_RU_End
L_RU_DownLoop:
000083DA 40 F0 3D 84 call F_Delay
000083DC 41 94 r2 = 0x0001
000083DD 1A D5 12 70 [P_Watchdog_Clear] = r2
000083DF 09 23 40 00 r1 -= 0x40
000083E1 19 D3 17 70 [P_DAC1] = r1
000083E3 09 43 00 80 cmp r1,0x8000
000083E5 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
000083E6 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
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