📄 hardware.lst
字号:
00008692 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008694 40 92 R1 =0x0000 //
00008695 11 93 01 00 R1 = [R_InterruptStatus] //
00008697 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
00008699 19 D3 01 00 [R_InterruptStatus] = R1 //
0000869B 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000869D 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000869E 40 92 R1 = 0x0000 // 24MHz Fosc
0000869F 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
000086A1 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
000086A2 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
000086A4 09 93 ED FC R1 = 0xfced // 15.625K
000086A6 19 D3 0A 70 [P_TimerA_Data]=R1
000086A8 09 93 A8 00 R1 = 0x00A8 //
000086AA 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
000086AC 09 93 FF FF R1 = 0xffff
000086AE 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000086B0 11 93 01 00 R1 = [R_InterruptStatus] //
000086B2 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
000086B4 19 D3 01 00 [R_InterruptStatus] = R1 //
000086B6 19 D3 10 70 [P_INT_Ctrl] = R1 //
000086B8 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
000086B9 60 92 R1=0x0020;
000086BA 19 D3 13 70 [P_SystemClock]=R1
000086BC 09 93 A8 00 R1 = 0x00A8; //
000086BE 19 D3 2A 70 [P_DAC_Ctrl]= R1
000086C0 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000086C1 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
000086C3 09 93 00 FE R1 = 0xfe00; // 24K
000086C5 19 D3 0A 70 [P_TimerA_Data] = R1;
000086C7 09 93 FF FF R1 = 0xffff
000086C9 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000086CB 11 93 01 00 R1 = [R_InterruptStatus] //
000086CD 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000086CF 19 D3 01 00 [R_InterruptStatus] = R1 //
000086D1 19 D3 10 70 [P_INT_Ctrl] = R1 //
000086D3 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
000086D4 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
000086D5 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
000086D7 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000086D8 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
000086DA 40 92 R1 = 0x0000 // Fosc/2
000086DB 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
000086DD 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
000086DF 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
000086E1 09 93 FF FF R1 = 0xffff
000086E3 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
000086E5 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
000086E6 46 92 R1 = 0x0006
000086E7 19 D3 2A 70 [P_DAC_Ctrl] = R1
000086E9 09 93 00 FE R1 = 0xFE00
000086EB 19 D3 0A 70 [P_TimerA_Data] = R1 //
000086ED 11 93 01 00 R1 = [R_InterruptStatus] //
000086EF 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
000086F1 19 D3 01 00 [R_InterruptStatus] = R1 //
000086F3 19 D3 10 70 [P_INT_Ctrl] = R1 //
000086F5 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
000086F6 09 93 A8 00 R1 = 0x00A8
000086F8 19 D3 2A 70 [P_DAC_Ctrl] = R1
000086FA 09 93 00 FE R1 = 0xFE00
000086FC 19 D3 0A 70 [P_TimerA_Data] = R1 //
000086FE 11 93 01 00 R1 = [R_InterruptStatus] //
00008700 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008702 19 D3 01 00 [R_InterruptStatus] = R1 //
00008704 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008706 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
00008707 09 93 A8 00 R1 = 0x00A8
00008709 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000870B 09 93 9A FD R1 = 0xFD9A
0000870D 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000870F 11 93 01 00 R1 = [R_InterruptStatus] //
00008711 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008713 19 D3 01 00 [R_InterruptStatus] = R1 //
00008715 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008717 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
00008718 09 93 A8 00 R1 = 0x00A8
0000871A 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000871C 09 93 00 FD R1 = 0xFD00
0000871E 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008720 11 93 01 00 R1 = [R_InterruptStatus] //
00008722 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008724 19 D3 01 00 [R_InterruptStatus] = R1 //
00008726 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008728 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
00008729 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000872A 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000872C 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000872D 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000872F 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
00008731 19 D3 0A 70 [P_TimerA_Data] = r1;
00008733 75 92 r1 = 0x0035; // ADINI should be open (107)
00008734 19 D3 15 70 [P_ADC_Ctrl] = r1;
00008736 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
00008738 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000873A 09 93 FF FF r1 = 0xffff;
0000873C 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
0000873E 11 93 01 00 R1 = [R_InterruptStatus] //
00008740 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
00008742 19 D3 01 00 [R_InterruptStatus] = R1 //
00008744 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008746 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
00008747 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
00008748 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000874A 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
0000874C 19 D3 0A 70 [P_TimerA_Data] = r1
0000874E 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
0000874F 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
00008750 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
00008752 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
00008754 19 D3 0A 70 [P_TimerA_Data] = r1;
00008756 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
00008757 90 D4 push r1,r2 to [sp]
00008758 11 93 17 70 r1=[P_DAC1]
0000875A 09 B3 C0 FF r1 &= ~0x003f
0000875C 09 43 00 80 cmp r1,0x8000
0000875E 0E 0E jb L_RU_NormalUp
0000875F 19 5E je L_RU_End
L_RU_DownLoop:
00008760 40 F0 C3 87 call F_Delay
00008762 41 94 r2 = 0x0001
00008763 1A D5 12 70 [P_Watchdog_Clear] = r2
00008765 09 23 40 00 r1 -= 0x40
00008767 19 D3 17 70 [P_DAC1] = r1
00008769 09 43 00 80 cmp r1,0x8000
0000876B 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
0000876C 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
0000876D 40 F0 C3 87 call F_Delay
0000876F 41 94 r2 = 0x0001
00008770 1A D5 12 70 [P_Watchdog_Clear] = r2
00008772 09 03 40 00 r1 += 0x40
00008774 19 D3 17 70 [P_DAC1] = r1
00008776 09 43 00 80 cmp r1, 0x8000
00008778 4C 4E jne L_RU_Loop
L_RU_End:
00008779 90 90 pop r1,r2 from [sp]
0000877A 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -