📄 hardware.lst
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0000834C 19 D3 13 70 [P_SystemClock]=R1
0000834E 09 93 A8 00 R1 = 0x00A8; //
00008350 19 D3 2A 70 [P_DAC_Ctrl]= R1
00008352 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008353 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
00008355 09 93 00 FE R1 = 0xfe00; // 24K
00008357 19 D3 0A 70 [P_TimerA_Data] = R1;
00008359 09 93 FF FF R1 = 0xffff
0000835B 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000835D 11 93 01 00 R1 = [R_InterruptStatus] //
0000835F 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
00008361 19 D3 01 00 [R_InterruptStatus] = R1 //
00008363 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008365 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00008366 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
00008367 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
00008369 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000836A 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
0000836C 40 92 R1 = 0x0000 // Fosc/2
0000836D 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000836F 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
00008371 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
00008373 09 93 FF FF R1 = 0xffff
00008375 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008377 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00008378 46 92 R1 = 0x0006
00008379 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000837B 09 93 00 FE R1 = 0xFE00
0000837D 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000837F 11 93 01 00 R1 = [R_InterruptStatus] //
00008381 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00008383 19 D3 01 00 [R_InterruptStatus] = R1 //
00008385 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008387 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00008388 09 93 A8 00 R1 = 0x00A8
0000838A 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000838C 09 93 00 FE R1 = 0xFE00
0000838E 19 D3 0A 70 [P_TimerA_Data] = R1 //
00008390 11 93 01 00 R1 = [R_InterruptStatus] //
00008392 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00008394 19 D3 01 00 [R_InterruptStatus] = R1 //
00008396 19 D3 10 70 [P_INT_Ctrl] = R1 //
00008398 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
00008399 09 93 A8 00 R1 = 0x00A8
0000839B 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000839D 09 93 9A FD R1 = 0xFD9A
0000839F 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083A1 11 93 01 00 R1 = [R_InterruptStatus] //
000083A3 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083A5 19 D3 01 00 [R_InterruptStatus] = R1 //
000083A7 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083A9 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
000083AA 09 93 A8 00 R1 = 0x00A8
000083AC 19 D3 2A 70 [P_DAC_Ctrl] = R1
000083AE 09 93 00 FD R1 = 0xFD00
000083B0 19 D3 0A 70 [P_TimerA_Data] = R1 //
000083B2 11 93 01 00 R1 = [R_InterruptStatus] //
000083B4 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000083B6 19 D3 01 00 [R_InterruptStatus] = R1 //
000083B8 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083BA 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
000083BB 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
000083BC 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
000083BE 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000083BF 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
000083C1 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000083C3 19 D3 0A 70 [P_TimerA_Data] = r1;
000083C5 75 92 r1 = 0x0035; // ADINI should be open (107)
000083C6 19 D3 15 70 [P_ADC_Ctrl] = r1;
000083C8 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000083CA 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000083CC 09 93 FF FF r1 = 0xffff;
000083CE 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000083D0 11 93 01 00 R1 = [R_InterruptStatus] //
000083D2 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
000083D4 19 D3 01 00 [R_InterruptStatus] = R1 //
000083D6 19 D3 10 70 [P_INT_Ctrl] = R1 //
000083D8 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000083D9 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000083DA 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000083DC 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
000083DE 19 D3 0A 70 [P_TimerA_Data] = r1
000083E0 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000083E1 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000083E2 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000083E4 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000083E6 19 D3 0A 70 [P_TimerA_Data] = r1;
000083E8 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000083E9 90 D4 push r1,r2 to [sp]
000083EA 11 93 17 70 r1=[P_DAC1]
000083EC 09 B3 C0 FF r1 &= ~0x003f
000083EE 09 43 00 80 cmp r1,0x8000
000083F0 0E 0E jb L_RU_NormalUp
000083F1 19 5E je L_RU_End
L_RU_DownLoop:
000083F2 40 F0 55 84 call F_Delay
000083F4 41 94 r2 = 0x0001
000083F5 1A D5 12 70 [P_Watchdog_Clear] = r2
000083F7 09 23 40 00 r1 -= 0x40
000083F9 19 D3 17 70 [P_DAC1] = r1
000083FB 09 43 00 80 cmp r1,0x8000
000083FD 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
000083FE 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
000083FF 40 F0 55 84 call F_Delay
00008401 41 94 r2 = 0x0001
00008402 1A D5 12 70 [P_Watchdog_Clear] = r2
00008404 09 03 40 00 r1 += 0x40
00008406 19 D3 17 70 [P_DAC1] = r1
00008408 09 43 00 80 cmp r1, 0x8000
0000840A 4C 4E jne L_RU_Loop
L_RU_End:
0000840B 90 90 pop r1,r2 from [sp]
0000840C 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
0000840D 90 D4 push r1,r2 to [sp]
//int off
0000840E 11 93 17 70 r1 = [P_DAC1]
00008410 09 B3 C0 FF r1 &= ~0x003F
00008412 0A 5E jz L_RD_End
L_RD_Loop:
00008413 40 F0 55 84 call F_Delay
00008415 41 94 r2 = 0x0001
00008416 1A D5 12 70 [P_Watchdog_Clear] = r2
00008418 09 23 40 00 r1 -= 0x40
0000841A 19 D3 17 70 [P_DAC1] = r1
0000841C 4A 4E jnz L_RD_Loop
L_RD_End:
//int fiq,irq
0000841D 90 90 pop r1,r2 from [sp]
0000841E 90 9A retf
.ENDP
//..............................................................
_SP_RampUpDAC2: .PROC
F_SP_RampUpDAC2:
0000841F 90 D4 push r1,r2 to [sp]
00008420 11 93 16 70 r1=[P_DAC2]
00008422 09 B3 C0 FF r1 &= ~0x003f
00008424 09 43 00 80 cmp r1,0x8000
00008426 0E 0E jb L_RU_NormalUp_
00008427 5D 5E je L_RU_End
L_RU_DownLoop_:
00008428 40 F0 55 84 call F_Delay
0000842A 41 94 r2 = 0x0001
0000842B 1A D5 12 70 [P_Watchdog_Clear] = r2
0000842D 09 23 40 00 r1 -= 0x40
0000842F 19 D3 16 70 [P_DAC2] = r1
00008431 09 43 00 80 cmp r1,0x8000
00008433 4C 4E jne L_RU_DownLoop_
L_RD_DownEnd_:
00008434 0C EE jmp L_RU_End_
L_RU_NormalUp_:
L_RU_Loop_:
00008435 40 F0 55 84 call F_Delay
00008437 41 94 r2 = 0x0001
00008438 1A D5 12 70 [P_Watchdog_Clear] = r2
0000843A 09 03 40 00 r1 += 0x40
0000843C 19 D3 16 70 [P_DAC2] = r1
0000843E 09 43 00 80 cmp r1, 0x8000
00008440 4C 4E jne L_RU_Loop_
L_RU_End_:
00008441 90 90 pop r1,r2 from [sp]
00008442 90 9A retf
.ENDP
//.............................................................
_SP_RampDnDAC2: .PROC
F_SP_RampDnDAC2:
//int off
00008443 90 D4 push r1,r2 to [sp]
00008444 11 93 16 70 r1 = [P_DAC2]
00008446 09 B3 C0 FF r1 &= ~0x003F
00008448 0A 5E jz L_RD_End_
L_RD_Loop_:
00008449 40 F0 55 84 call F_Delay
0000844B 41 94 r2 = 0x0001
0000844C 1A D5 12 70 [P_Watchdog_Clear] = r2
0000844E 09 23 40 00 r1 -= 0x40
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