📄 hardware.lst
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.define C_QueueSize 100
00000002 00 00 .VAR R_Queue
00000003 00 00 00 00 .DW C_QueueSize-1 DUP(0)
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00000066 00 00 .VAR R_ReadIndex
00000067 00 00 .VAR R_WriteIndex
000082C3 .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
000082C3 09 93 02 00 R1 = R_Queue
000082C5 40 94 R2 = 0
L_ClearQueueLoop?:
000082C6 D1 D4 [R1++] = R2
000082C7 09 43 66 00 cmp R1, R_Queue+C_QueueSize
000082C9 44 4E jne L_ClearQueueLoop?
000082CA 40 92 R1 = 0
000082CB 19 D3 66 00 [R_ReadIndex] = R1
000082CD 19 D3 67 00 [R_WriteIndex] = R1
000082CF 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
000082D0 12 95 66 00 R2 = [R_ReadIndex]
000082D2 12 45 67 00 cmp R2,[R_WriteIndex]
000082D4 0D 5E je L_RQ_QueueEmpty
000082D5 0A 05 02 00 R2 += R_Queue // get queue data address
000082D7 C2 92 R1 = [R2]
000082D8 12 95 66 00 R2 = [R_ReadIndex]
000082DA 41 04 R2 += 1
000082DB 0A 45 64 00 cmp R2, C_QueueSize
000082DD 01 4E jne L_RQ_NotQueueBottom
000082DE 40 94 R2 = 0
L_RQ_NotQueueBottom:
000082DF 1A D5 66 00 [R_ReadIndex] = R2
//r2 = 0x0000 // get queue data
000082E1 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
000082E2 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
000082E3 12 95 66 00 R2 = [R_ReadIndex]
000082E5 12 45 67 00 cmp R2,[R_WriteIndex]
000082E7 03 5E je L_RQ_QueueEmpty?
000082E8 0A 05 02 00 R2 += R_Queue // get queue data index
000082EA C2 92 R1 = [R2]
L_RQ_QueueEmpty?:
000082EB 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
000082EC 12 95 67 00 R2 = [R_WriteIndex] // put data to queue
000082EE 0A 05 02 00 R2 += R_Queue
000082F0 C2 D2 [R2] = R1
000082F1 12 95 67 00 R2 = [R_WriteIndex]
000082F3 41 04 R2 += 1
000082F4 0A 45 64 00 cmp R2, C_QueueSize
000082F6 01 4E jne L_WQ_NotQueueBottom
000082F7 40 94 R2 = 0
L_WQ_NotQueueBottom:
000082F8 1A D5 67 00 [R_WriteIndex] = R2
000082FA 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
000082FB 11 93 66 00 R1 = [R_ReadIndex]
000082FD 11 43 67 00 cmp R1,[R_WriteIndex]
000082FF 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
00008300 11 93 66 00 R1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
00008302 05 4E jnz L_TQ_JudgeCond2
00008303 11 93 67 00 R1 = [R_WriteIndex]
00008305 09 43 63 00 cmp R1, C_QueueSize-1 // Cond1
00008307 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
00008308 11 93 66 00 R1 = [R_ReadIndex]
0000830A 41 22 R1 -=1
0000830B 11 43 67 00 cmp R1,[R_WriteIndex]
0000830D 02 5E je L_TQ_QueueFull
0000830E 40 92 r1 = 0 // not Full, not empty
0000830F 90 9A retf
L_TQ_QueueFull:
00008310 41 92 r1 = 1 // full
00008311 90 9A retf
L_TQ_QueueEmpty:
00008312 42 92 r1 = 2 // empty
00008313 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
// or F_SACM_A2000_Initial:
// Note: The following functions are the partial code of original
// initial subroutine. (H/W setting part)
//
// Ex: F_SACM_A2000_Initial:
// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
00008314 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
00008315 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
00008317 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008318 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
0000831A 09 93 00 FD R1 = 0xfd00 // 16K
0000831C 19 D3 0A 70 [P_TimerA_Data] = R1
0000831E 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
00008320 19 D3 2A 70 [P_DAC_Ctrl] = R1
00008322 09 93 FF FF R1 = 0xffff
00008324 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008326 40 92 R1 =0x0000 //
00008327 11 93 01 00 R1 = [R_InterruptStatus] //
00008329 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
0000832B 19 D3 01 00 [R_InterruptStatus] = R1 //
0000832D 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000832F 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008330 40 92 R1 = 0x0000 // 24MHz Fosc
00008331 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
00008333 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008334 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
00008336 09 93 ED FC R1 = 0xfced // 15.625K
00008338 19 D3 0A 70 [P_TimerA_Data]=R1
0000833A 09 93 A8 00 R1 = 0x00A8 //
0000833C 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000833E 09 93 FF FF R1 = 0xffff
00008340 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
00008342 11 93 01 00 R1 = [R_InterruptStatus] //
00008344 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00008346 19 D3 01 00 [R_InterruptStatus] = R1 //
00008348 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000834A 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000834B 60 92 R1=0x0020;
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