📄 msp430x14x.h
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#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000) /* Capture mode: 1 - both edges */
/************************************************************
* Timer B
************************************************************/
#define TBIV_ (0x011E) /* Timer B Interrupt Vector Word */
const sfrw TBIV = TBIV_;
#define TBCTL_ (0x0180) /* Timer B Control */
sfrw TBCTL = TBCTL_;
#define TBCCTL0_ (0x0182) /* Timer B Capture/Compare Control 0 */
sfrw TBCCTL0 = TBCCTL0_;
#define TBCCTL1_ (0x0184) /* Timer B Capture/Compare Control 1 */
sfrw TBCCTL1 = TBCCTL1_;
#define TBCCTL2_ (0x0186) /* Timer B Capture/Compare Control 2 */
sfrw TBCCTL2 = TBCCTL2_;
#define TBCCTL3_ (0x0188) /* Timer B Capture/Compare Control 3 */
sfrw TBCCTL3 = TBCCTL3_;
#define TBCCTL4_ (0x018A) /* Timer B Capture/Compare Control 4 */
sfrw TBCCTL4 = TBCCTL4_;
#define TBCCTL5_ (0x018C) /* Timer B Capture/Compare Control 5 */
sfrw TBCCTL5 = TBCCTL5_;
#define TBCCTL6_ (0x018E) /* Timer B Capture/Compare Control 6 */
sfrw TBCCTL6 = TBCCTL6_;
#define TBR_ (0x0190) /* Timer B */
sfrw TBR = TBR_;
#define TBCCR0_ (0x0192) /* Timer B Capture/Compare 0 */
sfrw TBCCR0 = TBCCR0_;
#define TBCCR1_ (0x0194) /* Timer B Capture/Compare 1 */
sfrw TBCCR1 = TBCCR1_;
#define TBCCR2_ (0x0196) /* Timer B Capture/Compare 2 */
sfrw TBCCR2 = TBCCR2_;
#define TBCCR3_ (0x0198) /* Timer B Capture/Compare 3 */
sfrw TBCCR3 = TBCCR3_;
#define TBCCR4_ (0x019A) /* Timer B Capture/Compare 4 */
sfrw TBCCR4 = TBCCR4_;
#define TBCCR5_ (0x019C) /* Timer B Capture/Compare 5 */
sfrw TBCCR5 = TBCCR5_;
#define TBCCR6_ (0x019E) /* Timer B Capture/Compare 6 */
sfrw TBCCR6 = TBCCR6_;
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
#define CNTL1 (0x1000) /* Counter lenght 1 */
#define CNTL0 (0x0800) /* Counter lenght 0 */
#define TBSSEL2 (0x0400) /* unused */
#define TBSSEL1 (0x0200) /* Clock source 1 */
#define TBSSEL0 (0x0100) /* Clock source 0 */
#define TBCLR (0x0004) /* Timer B counter clear */
#define TBIE (0x0002) /* Timer B interrupt enable */
#define TBIFG (0x0001) /* Timer B interrupt flag */
#define TBSSEL_0 (0*0x0100) /* Clock Source: TBCLK */
#define TBSSEL_1 (1*0x0100) /* Clock Source: ACLK */
#define TBSSEL_2 (2*0x0100) /* Clock Source: SMCLK */
#define TBSSEL_3 (3*0x0100) /* Clock Source: INCLK */
#define CNTL_0 (0*0x0800) /* Counter lenght: 16 bit */
#define CNTL_1 (1*0x0800) /* Counter lenght: 12 bit */
#define CNTL_2 (2*0x0800) /* Counter lenght: 10 bit */
#define CNTL_3 (3*0x0800) /* Counter lenght: 8 bit */
#define SHR_0 (0*0x2000) /* Timer B Group: 0 - individually */
#define SHR_1 (1*0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2 (2*0x2000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3 (3*0x2000) /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0 (0*0x2000) /* Timer B Group: 0 - individually */
#define TBCLGRP_1 (1*0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2 (2*0x2000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3 (3*0x2000) /* Timer B Group: 3 - 1 group (all) */
/* Additional Timer B Control Register bits are defined in Timer A */
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
#define CLLD1 (0x0400) /* Compare latch load source 1 */
#define CLLD0 (0x0200) /* Compare latch load source 0 */
#define SLSHR_0 (0*0x0200) /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1 (1*0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2 (2*0x0200) /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3 (3*0x0200) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
#define CLLD_0 (0*0x0200) /* Compare latch load sourec : 0 - immediate */
#define CLLD_1 (1*0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define CLLD_2 (2*0x0200) /* Compare latch load sourec : 2 - up/down */
#define CLLD_3 (3*0x0200) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
/************************************************************
* Basic Clock Module
************************************************************/
#define DCOCTL_ (0x0056) /* DCO Clock Frequency Control */
sfrb DCOCTL = DCOCTL_;
#define BCSCTL1_ (0x0057) /* Basic Clock System Control 1 */
sfrb BCSCTL1 = BCSCTL1_;
#define BCSCTL2_ (0x0058) /* Basic Clock System Control 2 */
sfrb BCSCTL2 = BCSCTL2_;
#define MOD0 (0x01) /* Modulation Bit 0 */
#define MOD1 (0x02) /* Modulation Bit 1 */
#define MOD2 (0x04) /* Modulation Bit 2 */
#define MOD3 (0x08) /* Modulation Bit 3 */
#define MOD4 (0x10) /* Modulation Bit 4 */
#define DCO0 (0x20) /* DCO Select Bit 0 */
#define DCO1 (0x40) /* DCO Select Bit 1 */
#define DCO2 (0x80) /* DCO Select Bit 2 */
#define RSEL0 (0x01) /* Resistor Select Bit 0 */
#define RSEL1 (0x02) /* Resistor Select Bit 1 */
#define RSEL2 (0x04) /* Resistor Select Bit 2 */
#define XT5V (0x08) /* XT5V should always be reset */
#define DIVA0 (0x10) /* ACLK Divider 0 */
#define DIVA1 (0x20) /* ACLK Divider 1 */
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
#define XT2OFF (0x80) /* Enable XT2CLK */
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
#define DCOR (0x01) /* Enable External Resistor : 1 */
#define DIVS0 (0x02) /* SMCLK Divider 0 */
#define DIVS1 (0x04) /* SMCLK Divider 1 */
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
#define DIVM0 (0x10) /* MCLK Divider 0 */
#define DIVM1 (0x20) /* MCLK Divider 1 */
#define SELM0 (0x40) /* MCLK Source Select 0 */
#define SELM1 (0x80) /* MCLK Source Select 1 */
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
/*************************************************************
* Flash Memory
*************************************************************/
#define FCTL1_ (0x0128) /* FLASH Control 1 */
sfrw FCTL1 = FCTL1_;
#define FCTL2_ (0x012A) /* FLASH Control 2 */
sfrw FCTL2 = FCTL2_;
#define FCTL3_ (0x012C) /* FLASH Control 3 */
sfrw FCTL3 = FCTL3_;
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Devide Flash clock by: 2^0 */
#define FN1 (0x0002) /* Devide Flash clock by: 2^1 */
#define FN2 (0x0004) /* Devide Flash clock by: 2^2 */
#define FN3 (0x0008) /* Devide Flash clock by: 2^3 */
#define FN4 (0x0010) /* Devide Flash clock by: 2^4 */
#define FN5 (0x0020) /* Devide Flash clock by: 2^5 */
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from UART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
#define WAIT (0x0008) /* Wait flag for segment write */
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020) /* Flash Emergency Exit */
/************************************************************
* Comparator A
************************************************************/
#define CACTL1_ (0x0059) /* Comparator A Control 1 */
sfrb CACTL1 = CACTL1_;
#define CACTL2_ (0x005A) /* Comparator A Control 2 */
sfrb CACTL2 = CACTL2_;
#define CAPD_ (0x005B) /* Comparator A Port Disable */
sfrb CAPD = CAPD_;
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
#define CAIE (0x02) /* Comp. A Interrupt Enable */
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON (0x08) /* Comp. A enable */
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
#define CAEX (0x80) /* Comp. A Exchange Inputs */
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT (0x01) /* Comp. A Output */
#define CAF (0x02) /* Comp. A Enable Output Filter */
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24 (0x10)
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