startup.msa

Actions ucOS-II mp3方案源码,可以做参考

/*
*******************************************************************************
*                ACTOS AP
*        main ap of sdk 3.0
*
*        (c) Copyright, Actions Co,Ld.
*             All Right Reserved
*
*******************************************************************************
*/

PLL_Clock    EQU    0b8h;088H;90H;0A0H;0B0H;0C0H;    // 27MHz;33MHz;39MHz;45MHz;51MHz

        extern main

        rseg POWERUP 
        jp    start  
        rseg INTR
        di
        reti     
        rseg INIT 
start:    
        ld sp,3effh 
        call MCUInit 
        ld a,0xf4
        out (05h),a
        ld bc,0800h
        ld hl,4000h
        ld d,01fh
        ld e,00h
initdata0:
        ld a,d
        ld (hl),a
        inc hl
        ld  a,e
        ld (hl),a
        inc hl
        dec c
        jr  nz,initdata0
        djnz initdata0
        ld bc,0800h
        ld hl,5000h
        ld d,00h
        ld e,0f8h
initdata1:
        ld a,d
        ld (hl),a
        inc hl
        ld  a,e
        ld (hl),a 
        inc hl 
        dec c
        jr  nz,initdata1
        djnz initdata1
        ld bc,0800h
        ld hl,6000h
        ld d,0f8h
        ld e,00h
initdata2:
        ld a,d
        ld (hl),a
        inc hl
        ld  a,e
        ld (hl),a
        inc hl
        dec c
        jr  nz,initdata2
        djnz initdata2
        ld bc,800h
        ld hl,7000h
        ld d,0ffh
        ld e,0ffh
initdata3:
        ld a,d
        ld (hl),a
        inc hl
        ld  a,e
        ld (hl),a
        inc hl
        dec c
        jr  nz,initdata3
        djnz initdata3    
                    
        jp main   
MCUInit:     
        //clear watchdog 
        in      a,(4eh)
        or      08h
        out     (4eh),a
        ld      a,0x22
        out     (0x4e),a
        
        /*  Set A15 Normal        */
        ld      a,0x01        
        out     (0x04),a        
        
        /*Set interrupt mode，Disable all interrupt */
        di
        im      1                                     
        xor     a
        out     (0x27),a
        
        /* Enable MCU Clock Of High frequency OSC ,24MHZ */
        ld      a,0x85                                
        out     (0x40),a    
        /* Wait 64 Cycles */
        ld      b,0ffh
delay_for_Wait_64_Cycles:
        djnz    delay_for_Wait_64_Cycles
        
        //an    important factor
        //ld    a,21h                //mcu pll
        ld    a,11h                //hosc
        out    (00h),a                // mcu selcet 24MHz
        ld    b,0ffh
wait10240:
        djnz    wait10240
        
        ld    a,PLL_Clock
        out    (70h),a
        ld    b,0ffh
wait10241:
        djnz    wait10241    
        
        ld    a,0f3h
        out    (05h),a                //SET TO RESERVED VALUE
        
        /* Enable DMA Clock Of High frequency OSC ,12MHZ  */
        in      a,(0x04)
        or      0x08
        out     (0x04),a
        
        ld      a,0x00
        out     (0x3d),a   
        RET    
        end