📄 spmc65.inc
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P_IO_Opt: EQU $35 ; I/O slew rate control register.
C_IO_SLOWE: EQU %00000001 ; PB[7:6] slew rate enable selection.(A)
;
P_LVR_Opt: EQU $36 ; LVR Option
C_LVR_V40: EQU %00000001 ; LVR level select bit.(A)
;
P_PLL_Ctrl: EQU $37 ; PLL control register.
C_PLL_2M67: EQU %00000000 ; Set PLL 2.67MHz.
C_PLL_3M43: EQU %00000001 ; Set PLL 3.43MHz.
C_PLL_4M19: EQU %00000010 ; Set PLL 4.19MHz.
C_PLL_4M95: EQU %00000011 ; Set PLL 4.95MHz.
C_PLL_5M71: EQU %00000100 ; Set PLL 5.71MHz.
C_PLL_6M47: EQU %00000101 ; Set PLL 6.47MHz.
C_PLL_7M23: EQU %00000110 ; Set PLL 7.23MHz.
C_PLL_8M00: EQU %00000111 ; Set PLL 8.00MHz.
;
;-----------------------------------------------------------------------------------------------------
P_SPI_Ctrl0: EQU $38 ; SPI control register 0.
C_SPI_EN: EQU %10000000 ; enable Control bit.
C_SPI_MOD: EQU %01000000 ; operation Mode Master/Slave Mode.
C_SPI_SCKPHA: EQU %00100000 ; clock phase.
C_SPI_SCKPOL: EQU %00010000 ; clock polarity.
C_SPI_SPISMPS: EQU %00001000 ; sample mode selection bit for master mode.
C_SPICK_Div_128: EQU %00000101 ; CPU clock/128.
C_SPICK_Div_64: EQU %00000100 ; CPU clock/64.
C_SPICK_Div_32: EQU %00000011 ; CPU clock/32.
C_SPICK_Div_16: EQU %00000010 ; CPU clock/16.
C_SPICK_Div_8: EQU %00000001 ; CPU clock/8.
C_SPICK_Div_4: EQU %00000000 ; CPU clock/4.
;
P_SPI_Ctrl1: EQU $39 ; SPI control register 1.
C_SPI_SSBEN: EQU %10000000 ; control enable bit.
C_SPI_SWRST: EQU %01000000 ; software reset bit.
C_SAMPCK_Div_4: EQU %00000011 ; sampling clock Div/4.
C_SAMPCK_Div_2: EQU %00000010 ; sampling clock Div/2.
C_SAMPCK_Div_1: EQU %00000001 ; sampling clock Div/1.
C_SAMPDISABLE: EQU %00000000 ; no sampling.
;
P_SPI_Status: EQU $3A ; SPI status register.
C_SPI_CLRTXIF: EQU %10000000 ; clear transmit interrupt flag.
C_SPI_TXIEN: EQU %01000000 ; transmit interrupt enable/diable.
C_SPI_TXBF: EQU %00100000 ; transmission buffer full flag.
C_SPI_CLRRXIF: EQU %00000100 ; clear receive interrupt flag.
C_SPI_RXIEN: EQU %00000010 ; receive interrupt enable/diable.
C_SPI_BUFFull: EQU %00000001 ; buffer full and overwrite.
;
P_SPI_TxData: EQU $3B ; SPI Transmit data buffer.
P_SPI_RxData: EQU $3C ; SPI Receive data buffer.
;
;-----------------------------------------------------------------------------------------------------
P_IOE_Data: EQU $40 ; Port E data b0~b7.(A)
P_IOF_Data: EQU $41 ; Port F data b0~b7.(A)
P_IOE_Dir: EQU $42 ; Port E direction control b0~b7.(W)
P_IOF_Dir: EQU $43 ; Port F direction control b0~b7.(W)
P_IOE_Attrib: EQU $44 ; Port E attribute register b0~b7.(W)
P_IOF_Attrib: EQU $45 ; Port F attribute register b0~b7.(W)
;
;-----------------------------------------------------------------------------------------------------
P_UART_Ctrl: EQU $46 ; UART control register.
C_UART_RXIE: EQU %10000000 ; receive interrupt enable bit.
C_UART_TXIE: EQU %01000000 ; transmit interrupt enable bit.
C_UART_RXEN: EQU %00100000 ; receive function enable bit.
C_UART_TXEN: EQU %00010000 ; transmit function enable bit.
C_UART_SOFTRST: EQU %00001000 ; software reset.
C_UART_STOPSEL: EQU %00000100 ; stop bit length selection bit.
C_UART_PSEL: EQU %00000010 ; parity type selection bit.
C_UART_PEN: EQU %00000001 ; parity check or generation enable bit.
;
P_UART_Baud: EQU $47 ; UART baud rate divisor.
;
P_UART_Status: EQU $48 ; UART staus register.
C_UART_RXIF: EQU %10000000 ; receive interrupt flag.
C_UART_TXIF: EQU %01000000 ; transmit interrupt flag.
C_UART_BUSY: EQU %00100000 ; transmission in progress flag bit.
C_UART_OERR: EQU %00000100 ; overrun error flag bit.
C_UART_PERR: EQU %00000010 ; parity error flag bit.
C_UART_FERR: EQU %00000001 ; frame error flag bit.
;
P_UART_Data: EQU $49 ; UART data register.
;
;-----------------------------------------------------------------------------------------------------
P_IICS_Ctrl: EQU $4A ; IIC series and S+ series control register.
C_IICS_IICEN: EQU %10000000 ; IIC series interface enable bit.
C_IICS_SSEN: EQU %01000000 ; Sunplus series interface enable bit.
C_IICS_TXRXEN: EQU %00100000 ; IIC bus data output enable bit.
C_IICS_INTREN: EQU %00010000 ; IIC and S+ series interface interrupt enable bit.
C_IICS_ACKEN: EQU %00001000 ; IIC acknowledge enable bit.
C_IICS_SCK_2048: EQU %00000111 ; interface clock rate. Fsys/2048.
C_IICS_SCK_1024: EQU %00000110 ; interface clock rate. Fsys/1024.
C_IICS_SCK_512: EQU %00000101 ; interface clock rate. Fsys/512.
C_IICS_SCK_256: EQU %00000100 ; interface clock rate. Fsys/256.
C_IICS_SCK_128: EQU %00000011 ; interface clock rate. Fsys/128.
C_IICS_SCK_64: EQU %00000010 ; interface clock rate. Fsys/64.
C_IICS_SCK_32: EQU %00000001 ; interface clock rate. Fsys/32.
;
P_IICS_Status: EQU $4B ; IIC series and S+ series status register.
C_IICS_MXT: EQU %10000000 ; IIC master/slave mode selection or S+ 17/25 bit mode.
C_IICS_TXRXSEL: EQU %01000000 ; Tx/Rx selection bit.
C_IICS_BUSY: EQU %00100000 ; bus busy signal.
C_IICS_SIGGEN: EQU %00100000 ; IIC start/stop signal generation.
C_IICS_INTIF: EQU %00010000 ; IIC and S+ series interrupt flag bit.
C_IICS_ARBITRAT: EQU %00001000 ; IIC bus arbitration status.
C_IICS_FORMAT: EQU %00001000 ; S+ series data format.
C_IICS_AAS: EQU %00000100 ; I2C bus address-as-slave status flag or S+ series data foramt bit0.
C_IICS_AZERO: EQU %00000010 ; IIC address zero status flag.
C_IICS_LRB: EQU %00000001 ; IIC last-received bit status flag.
;
P_IICS_Data: EQU $4C ; IIC series and S+ series data register.
P_IICS_Address: EQU $4D ; IIC series and S+ series address bits.
P_IICS_HADDR: EQU $4E ; S+ series interface address [15:8].
P_IICS_MADDR: EQU $4F ; S+ series interface address [23:16].
;
;-----------------------------------------------------------------------------------------------------
P_DA_Ctrl: EQU $55 ; DA converter control register.
C_DA_EN: EQU %10000000 ; DA converter enable bit.
;
P_DA_DataLo: EQU $56 ; Converted D/A data[1:0] low.(R)
P_DA_DataHi: EQU $57 ; Converted D/A data[9:2] hi.(R)
;
;-----------------------------------------------------------------------------------------------------
P_CAP_Ctrl: EQU $58 ; Capture control.
C_CAP_OPT: EQU %10000000 ; Capture option control bit.(A)
C_CAP_IP4: EQU %01000000 ; Capture4 interrupt evoke polarity.
C_CAP_IP3: EQU %00100000 ; Capture3 interrupt evoke polarity.
C_CAP_IP2: EQU %00010000 ; Capture2 interrupt evoke polarity.
C_CAP_IP1: EQU %00001000 ; Capture1 interrupt evoke polarity.
C_CAP_IP0: EQU %00000100 ; Capture4 interrupt evoke polarity.
C_CAP1_ES: EQU %00000010 ; Polarity control of capture1 interrupt.
C_CAP0_ES: EQU %00000001 ; Polarity control of capture0 interrupt.
;
;-----------------------------------------------------------------------------------------------------
P_IOA_Buf: EQU $59
C_IOA_Buf7: EQU %10000000 ; PDA7: Data Latch of PORTA bit7.
C_IOA_Buf6: EQU %01000000 ; PDA6: Data Latch of PORTA bit6.
C_IOA_Buf5: EQU %00100000 ; PDA5: Data Latch of PORTA bit5.
C_IOA_Buf4: EQU %00010000 ; PDA4: Data Latch of PORTA bit4.
C_IOA_Buf3: EQU %00001000 ; PDA3: Data Latch of PORTA bit3.
C_IOA_Buf2: EQU %00000100 ; PDA2: Data Latch of PORTA bit2.
C_IOA_Buf1: EQU %00000010 ; PDA1: Data Latch of PORTA bit1.
C_IOA_Buf0: EQU %00000001 ; PDA0: Data Latch of PORTA bit0.
P_IOB_Buf: EQU $5A
C_IOB_Buf7: EQU %10000000 ; PDB7: Data Latch of PORTB bit7.
C_IOB_Buf6: EQU %01000000 ; PDB6: Data Latch of PORTB bit6.
C_IOB_Buf5: EQU %00100000 ; PDB5: Data Latch of PORTB bit5.
C_IOB_Buf4: EQU %00010000 ; PDB4: Data Latch of PORTB bit4.
C_IOB_Buf3: EQU %00001000 ; PDB3: Data Latch of PORTB bit3.
C_IOB_Buf2: EQU %00000100 ; PDB2: Data Latch of PORTB bit2.
C_IOB_Buf1: EQU %00000010 ; PDB1: Data Latch of PORTB bit1.
C_IOB_Buf0: EQU %00000001 ; PDB0: Data Latch of PORTB bit0.
P_IOC_Buf: EQU $5B
C_IOC_Buf7: EQU %10000000 ; PDC7: Data Latch of PORTC bit7.
C_IOC_Buf6: EQU %01000000 ; PDC6: Data Latch of PORTC bit6.
C_IOC_Buf5: EQU %00100000 ; PDC5: Data Latch of PORTC bit5.
C_IOC_Buf4: EQU %00010000 ; PDC4: Data Latch of PORTC bit4.
C_IOC_Buf3: EQU %00001000 ; PDC3: Data Latch of PORTC bit3.
C_IOC_Buf2: EQU %00000100 ; PDC2: Data Latch of PORTC bit2.
C_IOC_Buf1: EQU %00000010 ; PDC1: Data Latch of PORTC bit1.
C_IOC_Buf0: EQU %00000001 ; PDC0: Data Latch of PORTC bit0.
P_IOD_Buf: EQU $5C
C_IOD_Buf7: EQU %10000000 ; PDD7: Data Latch of PORTD bit7.
C_IOD_Buf6: EQU %01000000 ; PDD6: Data Latch of PORTD bit6.
C_IOD_Buf5: EQU %00100000 ; PDD5: Data Latch of PORTD bit5.
C_IOD_Buf4: EQU %00010000 ; PDD4: Data Latch of PORTD bit4.
C_IOD_Buf3: EQU %00001000 ; PDD3: Data Latch of PORTD bit3.
C_IOD_Buf2: EQU %00000100 ; PDD2: Data Latch of PORTD bit2.
C_IOD_Buf1: EQU %00000010 ; PDD1: Data Latch of PORTD bit1.
C_IOD_Buf0: EQU %00000001 ; PDD0: Data Latch of PORTD bit0.
P_IOE_Buf: EQU $5D
C_IOE_Buf7: EQU %10000000 ; PDE7: Data Latch of PORTE bit7.
C_IOE_Buf6: EQU %01000000 ; PDE6: Data Latch of PORTE bit6.
C_IOE_Buf5: EQU %00100000 ; PDE5: Data Latch of PORTE bit5.
C_IOE_Buf4: EQU %00010000 ; PDE4: Data Latch of PORTE bit4.
C_IOE_Buf3: EQU %00001000 ; PDE3: Data Latch of PORTE bit3.
C_IOE_Buf2: EQU %00000100 ; PDE2: Data Latch of PORTE bit2.
C_IOE_Buf1: EQU %00000010 ; PDE1: Data Latch of PORTE bit1.
C_IOE_Buf0: EQU %00000001 ; PDE0: Data Latch of PORTE bit0.
P_IOF_Buf: EQU $5E
C_IOF_Buf7: EQU %10000000 ; PDF7: Data Latch of PORTF bit7.
C_IOF_Buf6: EQU %01000000 ; PDF6: Data Latch of PORTF bit6.
C_IOF_Buf5: EQU %00100000 ; PDF5: Data Latch of PORTF bit5.
C_IOF_Buf4: EQU %00010000 ; PDF4: Data Latch of PORTF bit4.
C_IOF_Buf3: EQU %00001000 ; PDF3: Data Latch of PORTF bit3.
C_IOF_Buf2: EQU %00000100 ; PDF2: Data Latch of PORTF bit2.
C_IOF_Buf1: EQU %00000010 ; PDF1: Data Latch of PORTF bit1.
C_IOF_Buf0: EQU %00000001 ; PDF0: Data Latch of PORTF bit0.
C_RAM_ADDR: EQU $60 ; RAM Start Address.
C_STACK_BOTTOM: EQU $0FF ; Stack Bottom Address.
.ENDIF
.IFDEF SPMC65P2104Ax
;=======================================================================
;SPMC65P2104A Input/Output Ports and Data Direction Registers
;=======================================================================
P_IOA_Data: EQU $00 ; Port A data b0~b7(A)
P_IOB_Data: EQU $01 ; Port B data b1,b3~b6(A)
P_IOA_Dir: EQU $04 ; Port A direction control b0~b7(W), 0=In, 1=Out
P_IOB_Dir: EQU $05 ; Port B direction control b1,b3~b6(W)
P_IOA_Attrib: EQU $08 ; Port A attribute register b0~b7(W)
P_IOB_Attrib: EQU $09 ; Port B attribute register b1,b3~b6(W)
;
;-----------------------------------------------------------------------------------------------------
P_INT_Flag0: EQU $0C ; Interrupt Flag 0.(A)
C_INT_ADIF: EQU %10000000 ; A/D INT flag bit.(A)
C_INT_WDIF: EQU %01000000 ; WDT INT flag bit.(A)
C_INT_IRQ1F: EQU %00000010 ; IRQ1 INT flag bit.(A)
C_INT_IRQ0F: EQU %00000001 ; IRQ0 INT flag bit.(A)
;
P_INT_Ctrl0: EQU $0D ; Interrupt control 0.(A)
C_INT_ADIE: EQU %10000000 ; A/D INT enable bit.(A)
C_INT_WDIE: EQU %01000000 ; WDT INT enable bit.(A)
C_INT_IRQ1E: EQU %00000001 ; IRQ1 INT enable bit.(A)
C_INT_IRQ0E: EQU %00000001 ; IRQ0 INT enable bit.(A)
;
P_INT_Flag1: EQU $0E ; Interrupt flag 1.
C_INT_CAP1IF: EQU %10000000 ; Capture1 INT flag bit.(A)
C_INT_T1OIF: EQU %00000010 ; Timer1 overflow INT flag bit.(A)
C_INT_T0OIF: EQU %00000001 ; Timer0 overflow INT flag bit.(A)
;
P_INT_Ctrl1: EQU $0F ; Interrupt control 1.
C_INT_CAP1IE: EQU %10000000 ; Capture1 INT enable bit.(A)
C_INT_T1OIE: EQU %00000010 ; Timer1 overflow INT enable bit.(A)
C_INT_T0OIE: EQU %00000001 ; Timer0 overflow INT enable bit.(A)
;
P_INT_Flag2: EQU $26 ; Interrupt flag 2.
C_INT_TVALIF: EQU %00100000 ; Timer Base interrupt flag.
;
P_INT_Ctrl2: EQU $27 ; Interrupt control 2.
C_INT_TVALIE: EQU %00100000 ; Timer Base interrupt enable bit.
;
P_WDT_Clr: EQU $10 ; Watchdog clear register.(W), $55= clear
C_WDT_Clr: EQU $55 ; Write '55' to clear this register.
;
;-----------------------------------------------------------------------------------------------------
P_TMR0_1_Ctrl0: EQU $11 ; Timer0/1 control 0.
C_T112B_PWM: EQU %01110000 ; Timer1 Function as 12 Bit PWM
C_T116B_CAP: EQU %01100000 ; Timer1 Function as 16 Bit Capture
C_T116B_COMP: EQU %01010000 ; Timer1 Function as 16 Bit Compare
C_T116B_Timer: EQU %01000000 ; Timer1 Function as 16 Bit Timer
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