📄 spmc65.inc
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;---------------------------------
;SPMC65P2404Ax .EQU 1
;---------------------------------
;; *********************************************************************
;; *** Sunplus Technology co., Ltd. ***
;; *** Header Name : SPMC65.inc ***
;; *** Applied Body : SPMC652PH0A,ECMC653SPMC65P2404A, ***
;; *** SPMC65P2104A,SPMC65P2204A,SPMC65P2408A ***
;; *** Purpose : Define all hardware,Registers and ports. ***
;; *** Programmer : Darrell Yang ***
;; *** redactor : ***
;; *** Data : 2004/11/05 V1.04 ***
;; *********************************************************************
.IFDEF SPMC652PH0Ax
;=======================================================================
;SPMC652PH0A Input/Output Ports and Data Direction Registers
;=======================================================================
P_IOA_Data: EQU $00 ; Port A data b0~b7(A)
P_IOB_Data: EQU $01 ; Port B data b0~b5(A)
P_IOC_Data: EQU $02 ; Port C data b0~b7(A)
P_IOD_Data: EQU $03 ; Port D data b0~b3(A)
P_IOA_Dir: EQU $04 ; Port A direction control b0~b7(W), 0=In, 1=Out
P_IOB_Dir: EQU $05 ; Port B direction control b0~b7(W)
P_IOC_Dir: EQU $06 ; Port C direction control b0~b7(W)
P_IOD_Dir: EQU $07 ; Port D direction control b0~b3(W)
P_IOA_Attrib: EQU $08 ; Port A attribute register b0~b7(W)
P_IOB_Attrib: EQU $09 ; Port B attribute register b0~b7(W)
P_IOC_Attrib: EQU $0A ; Port C attribute register b0~b7(W)
P_IOD_Attrib: EQU $0B ; Port D attribute register b0~b3(W)
P_INT_Flag0: EQU $0C ; Interrupt Flag 0.(A)
C_INT_T1OIF: EQU %10000000 ; Timer1 overflow INT flag bit.(A)
C_INT_ADIF: EQU %01000000 ; A/D INT flag bit.(A)
C_INT_WDIF: EQU %00100000 ; WDT INT flag bit.(A)
C_INT_RTIF: EQU %00010000 ; Real Time INT flag bit.(A)
C_INT_T0OIF: EQU %00001000 ; Timer0 overflow INT flag bit.(A)
C_INT_IRQ2F: EQU %00000100 ; IRQ2 INT flag bit.(A)
C_INT_IRQ1F: EQU %00000010 ; IRQ1 INT flag bit.(A)
C_INT_IRQ0F: EQU %00000001 ; IRQ0 INT flag bit.(A)
;
P_INT_Ctrl0: EQU $0D ; Interrupt control 0.(A)
C_INT_T1OIE: EQU %10000000 ; Timer1 overflow INT enable bit.(A)
C_INT_ADIE: EQU %01000000 ; A/D INT enable bit.(A)
C_INT_WDIE: EQU %00100000 ; WDT INT enable bit.(A)
C_INT_RTIE: EQU %00010000 ; Real Time INT enable bit.(A)
C_INT_T0OIE: EQU %00001000 ; Timer0 overflow INT enable bit.(A)
C_INT_IRQ2E: EQU %00000100 ; IRQ2 INT enable bit.(A)
C_INT_IRQ1E: EQU %00000010 ; IRQ1 INT enable bit.(A)
C_INT_IRQ0E: EQU %00000001 ; IRQ0 INT enable bit.(A)
;
P_INT_Flag1: EQU $0E ; Interrupt flag 1.
C_INT_T2OIF: EQU %10000000 ; Timer2 overflow INT flag bit.(A)
C_INT_CAP2IF: EQU %00001000 ; Capture2 INT flag bit.(A)
C_INT_CAP1IF: EQU %00000100 ; Capture1 INT flag bit.(A)
C_INT_CMP0IF: EQU %00000001 ; Comparator0 INT flag bit.(A)
;
P_INT_Ctrl1: EQU $0F ; Interrupt control 1.
C_INT_T2OIE: EQU %10000000 ; Timer2 overflow INT enable bit.(A)
C_INT_CAP2IE: EQU %00001000 ; Capture2 INT enable bit.(A)
C_INT_CAP1IE: EQU %00000100 ; Capture1 INT enable bit.(A)
C_INT_CMP0IE: EQU %00000001 ; Comparator0 INT enable bit.(A)
;
P_WDT_Clr: EQU $10 ; Watchdog clear register.(W), $55= clear
C_WDT_Clr: EQU $55 ; Writing '55' to this register.
;
P_TMR0_Ctrl: EQU $11 ; Timer0 control.
C_TMR0_T0EN: EQU %10000000 ; Timer0 auto-reload enable bit.(A)
; Prescaler of Timer0.(A)
C_TMR0_PS_1: EQU %00000000 ; 000:2^0
C_TMR0_PS_2: EQU %00010000 ; 001:2^1
C_TMR0_PS_4: EQU %00100000 ; 010:2^2
C_TMR0_PS_8: EQU %00110000 ; 011:2^3
C_TMR0_PS_16: EQU %01000000 ; 100:2^4
C_TMR0_PS_32: EQU %01010000 ; 101:2^5
C_TMR0_PS_64: EQU %01100000 ; 110:2^6
C_TMR0_PS_128: EQU %01110000 ; 111:2^7
C_TMR0_RTCS: EQU %00001000 ; Timer0 real time clock source select.(A)
C_TMR0_TCS: EQU %00000100 ; Timer0 clock source select.(A)
; Selection bits of Real Timer Interrupt Rate.(A)
C_TMR0_RT_2048: EQU %00000000 ; Divisor 2048.
C_TMR0_RT_4096: EQU %00000001 ; Divisor 4096.
C_TMR0_RT_8192: EQU %00000010 ; Divisor 8192.
C_TMR0_RT_16384:EQU %00000011 ; Divisor 16384.
;
P_TMR0_Cnt: EQU $12 ; Timer0 Counter register.(R)
P_TMR0_Preload: EQU $12 ; Timer0 preload register.(W)
P_TMR1_Ctrl: EQU $13 ; Timer1 Control.(A)
C_TMR1_T1EN: EQU %10000000 ; Timer1 auto-reload enable bit.(A)
; Prescaler of Timer1.(A)
C_TMR1_PS_1: EQU %00000000 ; 000:2^0
C_TMR1_PS_2: EQU %00010000 ; 001:2^1
C_TMR1_PS_4: EQU %00100000 ; 010:2^2
C_TMR1_PS_8: EQU %00110000 ; 011:2^3
C_TMR1_PS_16: EQU %01000000 ; 100:2^4
C_TMR1_PS_32: EQU %01010000 ; 101:2^5
C_TMR1_PS_64: EQU %01100000 ; 110:2^6
C_TMR1_PS_128: EQU %01110000 ; 111:2^7
C_TMR1_TCS: EQU %00000100 ; Timer1 clock source select.(A)
;
P_TMR1_Cnt: EQU $14 ; Timer1 Counter register.(R)
P_TMR1_Preload: EQU $14 ; Timer1 Counter register.(W)
P_TMR2_Ctrl: EQU $15 ; Timer2 Control.(A)
C_TMR2_T2EN: EQU %10000000 ; Timer2 auto-reload enable bit.(A)
C_TMR2_SYNC: EQU %01000000 ; Timer2 clock synchronization control bit.(A)
; Clock source select
C_TMR2_CPU2: EQU %00000100 ; Set CPU/2 as timer2 clock source
C_TMR2_CPU256: EQU %00001000 ; Set CPU/256 as timer2 clock source
C_TMR2_32768: EQU %00001100 ; Set 32768Hz as timer2 clock source
C_TMR2_1024: EQU %00000001 ; Set 1024Hz as timer2 clock source
C_TMR2_T1OF: EQU %00000010 ; Set timer1 overflow as timer2 clock source
C_TMR2_EXTCLK: EQU %00000011 ; Set external clock(PB2) as timer2 clock source
;
P_TMR2_CntLo: EQU $16 ; Timer2 low byte counter.(R)
P_TMR2_PreloadLo: EQU $16 ; Timer2 preload low byte counter.(W)
P_TMR2_CntHi: EQU $17 ; Timer2 high byte counter.(R)
P_TMR2_PreloadHi: EQU $17 ; Timer2 preload high byte counter.(W)
P_PWMDAC_Ctrl: EQU $18 ; PWM/DAC control.(A)
C_DAC_DAE: EQU %10000000 ; DA converter enable bit.(A)
C_PWM_PWMOD: EQU %01000000 ; PWM0&1 cascade mode select bit.(A)
C_PWM_PULSE1: EQU %00100000 ; PWM1 pulse mode select bit.(A)
C_PWM_PULSE0: EQU %00010000 ; PWM0 pulse mode select bit.(A)
C_PWM_PWMS1: EQU %00001000 ; PWM1 type select bit.(A)
C_PWM_PWME1: EQU %00000100 ; PWM1 enable bit.(A)
C_PWM_PWMC0: EQU %00000010 ; PWM0 clock select bit.(A)
C_PWM_PWME0: EQU %00000001 ; PWM0 enable bit.(A)
;
P_DAC_DataHi: EQU $19 ; high 8-bit DA Data register.(A)
P_DAC_DataLo: EQU $1A ; low 2-bit DA Data register.(A)
P_PWM0_Data: EQU $1B ; 8-bit PWM0 Wave Duty Cycle.(A)
P_PWM1_Data: EQU $1C ; 8-bit PWM1 Wave Duty Cycle.(A)
P_AD_Ctrl0: EQU $20 ; A/D Converter control 0.
C_AD_En: EQU %10000000 ; ADC enable control.(A)
; ADC Channel Selection.(A)
C_AD_Ch0: EQU %00000000 ; 000:channel 0.
C_AD_Ch1: EQU %00010000 ; 001:channel 1.
C_AD_Ch2: EQU %00100000 ; 010:channel 2.
C_AD_Ch3: EQU %00110000 ; 011:channel 3.
C_AD_Ch4: EQU %01000000 ; 100:channel 4.
C_AD_Ch5: EQU %01010000 ; 101:channel 5.
C_AD_Ch6: EQU %01100000 ; 110:channel 6.
C_AD_Ch7: EQU %01110000 ; 111:channel 7.
; AD clock select.(A)
C_AD_CS_1: EQU %00000000 ; 00=Fcpu/1.
C_AD_CS_4: EQU %00000100 ; 01=Fcpu/4.
C_AD_CS_8: EQU %00001000 ; 10=Fcpu/8.
C_AD_CS_16: EQU %00001100 ; 11=Fcpu/16.
C_AD_Rdy: EQU %00000001 ; ADC Status Bit.(R)
C_AD_Start: EQU %00000000 ; ADC Conversion Start Bit.(W)
;
P_AD_Ctrl1: EQU $21 ; A/D Converter control1.
C_AD_CE: EQU %10000000 ; ADC power control bit.(A)
; A/D channel configuration control bits.
C_AD_Pin0: EQU %00000000 ; A/D channel 0.(A)
C_AD_Pin1: EQU %00010000 ; A/D channel 1. AD0(A)
C_AD_Pin2: EQU %00100000 ; A/D channel 2. AD0,AD1(A)
C_AD_Pin3: EQU %00110000 ; A/D channel 3. AD0,AD1,AD2(A)
C_AD_Pin4: EQU %01000000 ; A/D channel 4. AD0,AD1,AD2,AD3(A)
C_AD_Pin5: EQU %01010000 ; A/D channel 5. AD0,AD1,AD2,AD3,AD4(A)
C_AD_Pin6: EQU %01100000 ; A/D channel 6. AD0,AD1,AD2,AD3,AD4,AD5,(A)
C_AD_Pin7: EQU %01110000 ; A/D channel 7. AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7(A)
C_AD_VRB: EQU %00001000 ; ADC bottom voltage source select bit.(A)
; A/D top reference voltage input.
C_AD_IRefV: EQU 00000010B ; Internal reference voltage.(2.0V)
;
P_AD_DataLo: EQU $22 ; Converted A/D data[1:0] low.(R)
P_AD_DataHi: EQU $23 ; Converted A/D data[9:2] hi.(R)
P_BUZ_Ctrl: EQU $24 ; Buzzer Control.
C_BUZ_BEN: EQU %10000000 ; Buzzer enable bit.(A)
;Buzzer frequency select bits.(A)
C_BUZ_Div_64: EQU %00000000 ; 000:Fto/2^6.
C_BUZ_Div_128: EQU %00000001 ; 001:Fto/2^7.
C_BUZ_Div_256: EQU %00000010 ; 010:Fto/2^8.
C_BUZ_Div_512: EQU %00000011 ; 011:Fto/2^9.
C_BUZ_Div_1024: EQU %00000100 ; 100:Fto/2^10.
C_BUZ_Div_2048: EQU %00000101 ; 101:Fto/2^11.
C_BUZ_Div_4096: EQU %00000110 ; 110:Fto/2^12.
C_BUZ_Div_8192: EQU %00000111 ; 111:Fto/2^13.
C_BUZ_Div_4: EQU %00001000 ; 1000:Fto/2^2.
C_BUZ_Div_8: EQU %00001001 ; 1001:Fto/2^3.
C_BUZ_Div_16: EQU %00001010 ; 1001:Fto/2^4.
C_BUZ_Div_32: EQU %00001011 ; 1001:Fto/2^5.
;
P_CMP0_Ctrl: EQU $25 ; Comparator0 control.
C_CMP0_RS: EQU %00001000 ; Comparator0 Reference Source for PC1.(A)
C_CMP0_ES: EQU %00000100 ; Comparator0 Event Selection bit of PC1.(A)
C_CMP0_En: EQU %00000010 ; Comparator0 Function Enable Control bit of PC1.(A)
C_CMP0_R: EQU %00000001 ; Comparsyot0 Result bit of PC1.(R)
;
P_CAP_Ctrl: EQU $26 ; Capture control
C_CAP_Opt: EQU %10000000 ; Capture option control bit.(A)
C_CAP2_ES: EQU %00100000 ; Polarity control of capture2 interrupt on PB6.(A)
C_CAP2_EN: EQU %00010000 ; Capture2 enable bit.(A)
C_CAP1_ES: EQU %00001000 ; Polarity control of capture1 interrupt on PB1.(A)
C_CAP1_EN: EQU %00000100 ; Capture1 enable bit.(A)
;
P_CAP1A_Data: EQU $29 ; Capture 1A data register.(R)
P_CAP1B_Data: EQU $2A ; Capture 1B data register.(R)
P_CAP2A_DataLo: EQU $2B ; Capture 2A low byte data register.(R)
P_CAP2A_DataHi: EQU $2C ; Capture 2A high byte data register.(R)
P_CAP2B_DataLo: EQU $2D ; Capture 2B low byte data register.(R)
P_CAP2B_DataHi: EQU $2E ; Capture 2B high byte data register.(R)
P_IDAW: EQU $3E ; Index addr write.(W)
P_IDDW: EQU $3F ; Index data write.(W)
P_IOE_Data: EQU $40 ; Port E data b0~b7(A)
P_IOE_Dir: EQU $41 ; Port E direction control b0~b7(W), 0=In, 1=Out
P_IOE_Attrib: EQU $42 ; Port E attribute register b0~b7(W)
P_IOF_Data: EQU $43 ; Port F data b0~b7(A)
P_IOF_Dir: EQU $44 ; Port F direction control b0~b7(W), 0=In, 1=Out
P_IOF_Attrib: EQU $45 ; Port F attribute register b0~b7(W)
P_LCD_Ctrl: EQU $50 ; LCD control
; LCD operation mode Selection.(A)
C_LCD_LcdOff: EQU %00000000 ; LCD off mode
C_LCD_Normal: EQU %00100000 ; LCD normal mode
C_LCD_AllOn: EQU %01000000 ; LCD all on mode
C_LCD_AllOff: EQU %01100000 ; LCD all off mode
; LCD Bias Selection.(A)
C_LCD_2Bias: EQU %00000000 ; LCD 1/2 bias
C_LCD_3Bias: EQU %00001000 ; LCD 1/3 bias
C_LCD_4Bias: EQU %00010000 ; LCD 1/4 bias
; LCD duty Selection.(A)
C_LCD_2Duty: EQU %00000000 ; LCD 1/2 duty
C_LCD_3Duty: EQU %00000001 ; LCD 1/3 duty
C_LCD_4Duty: EQU %00000010 ; LCD 1/4 duty
C_LCD_5Duty: EQU %00000011 ; LCD 1/5 duty
C_LCD_6Duty: EQU %00000100 ; LCD 1/6 duty
;
P_LCD_VLCD: EQU $51 ; LCD VLCD select
;-----------------------------------------------------------------------------------------------------
; Index Access Register
P_SYS_Ctrl: EQU $30 ; System control.
C_SCR_POR: EQU %10000000 ; Power On Reset Flag.(A)
C_SCR_ERST: EQU %01000000 ; External Reset Flag.(A)
C_SCR_LVR1: EQU %00100000 ; Low Voltage Reset Flag1.(A)
C_SCR_LVR0: EQU %00010000 ; Low Voltage Reset Flag0.(A)
C_SCR_WDTR: EQU %00001000 ; WDT Reset Flag.(A)
C_SCR_IAR: EQU %00000100 ; Illegal Address Reset Flag.(A)
C_SCR_IIR: EQU %00000001 ; Illegal instruction reset.(A)
;
P_STOP_Ctrl: EQU $31 ; Stop Control.(W)
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