📄 initcpu.s
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@----------------------------------------------------
@Copyright (C), 2005-2008, lst.
@版权所有 (C), 2005-2008, lst.
@所属模块: CPU初始化
@作者： lst
@版本： V1.00
@初始版本完成日期：2008-08-30
@文件描述: CPU初始化必须用汇编语言实现的部分
@其他说明: 无
@修订历史:
@ 2. ...
@ 1. 日期:
@ 作者:
@ 新版本号：
@ 修改说明:
@------------------------------------------------------
.include "./djyos/kernel/rominit/memcfg.a"
@.equ M_DIV, 120 /* 用于优龙10M晶振 */
@.equ P_DIV, 8
@.equ S_DIV, 1
.equ M_DIV, 56 /* Fin=8MHz Fout=64MHz */
.equ P_DIV, 2
.equ S_DIV, 1
@ Pre-defined constants
.equ USERMODE, 0x10
.equ SYSMODE, 0x1f
.equ FIQMODE, 0x11
.equ IRQMODE, 0x12
.equ SVCMODE, 0x13
.equ ABORTMODE, 0x17
.equ UNDEFMODE, 0x1b
.equ MODEMASK, 0x1f
.equ NOINT, 0xc0
.equ NOIRQ, 0x80
.equ NOFIQ, 0x40
.equ rWTCON, 0x01D30000
.equ rPLLCON, 0x01D80000
.equ rLOCKTIME, 0x01D8000C
.equ rCLKCON, 0x01D80004
.equ rBDIDES0, 0x01F80008
.equ rBDIDES1, 0x01F80028
.equ rREFRESH, 0x01C80024
.equ rBWSCON, 0x01c80000
.global _start
.extern load_preload @ 加载程序，在C中定义
.extern FIQ_stack
.extern IRQ_stack_bottom
.extern Abort_stack
.extern Undef_stack
.extern SVC_stack
.extern USR_stack
.text
_start:
b reset_start @ handlerReset
b except_undef @ handlerUndef
b except_swi @ SWI interrupt handler
b except_pabort @ handlerPAbort
b except_dabort @ handlerDAbort
b . @ handlerReserved
subs pc,lr,#4
subs pc,lr,#4
@***IMPORTANT NOTE***
@if the H/W vectored interrupt mode is disable,The above two instructions
@should be changed like below,to work-around with H/W bug of S3C44B0X
@interrupt controller.
@subs pc,lr,#4
@subs pc,lr,#4
@S3C44B0X的向量模式中断向量地址，固定在0x20处，只适用于IRQ。
@每个向量4字节，可以放一条跳转指令
.org 0x20
VECTOR_BRANCH:
ldr pc,=HandlerEINT0 @ 0x20
ldr pc,=HandlerEINT1
ldr pc,=HandlerEINT2
ldr pc,=HandlerEINT3
ldr pc,=HandlerEINT4567
ldr pc,=HandlerTICK @ 0x34
b .
b .
ldr pc,=HandlerZDMA0 @ 0x40
ldr pc,=HandlerZDMA1
ldr pc,=HandlerBDMA0
ldr pc,=HandlerBDMA1
ldr pc,=HandlerWDT
ldr pc,=HandlerUERR01 @ 0x54
b .
b .
ldr pc,=HandlerTIMER0 @ 0x60
ldr pc,=HandlerTIMER1
ldr pc,=HandlerTIMER2
ldr pc,=HandlerTIMER3
ldr pc,=HandlerTIMER4
ldr pc,=HandlerTIMER5 @ 0x74
b .
b .
ldr pc,=HandlerURXD0 @ 0x80
ldr pc,=HandlerURXD1
ldr pc,=HandlerIIC
ldr pc,=HandlerSIO
ldr pc,=HandlerUTXD0
ldr pc,=HandlerUTXD1 @ 0x94
b .
b .
ldr pc,=HandlerRTC @ 0xa0
b .
b .
b .
b .
b .
b .
b .
ldr pc,=HandlerADC @ 0xc0
except_undef: @ 未定义指令异常
b .
except_swi: @ SWI异常
b .
except_pabort: @ 取址异常
b .
except_dabort: @ 取数据异常
b .
reset_start: @复位向量地址
mrs r0,cpsr @取CPSR
bic r0,r0,#MODEMASK @清模式位
orr r1,r0,#SVCMODE|NOINT @设置为管理态，并禁止中断
msr cpsr_cxsf,r1 @切换到管理态,可防止意外返回0地址时出错.
ldr r0,=rWTCON @禁止看门狗
ldr r1,=0x0
str r1,[r0]
ldr r0,=rPLLCON @设定工作时钟(PLL倍频)
ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) @ Fin=8MHz Fout=64MHz
str r1,[r0]
ldr r0,=rCLKCON @允许所有外设时钟
ldr r1,=0x7ff8 @7ff8是复位默认值，当程序意外返回0时重新初始化
str r1,[r0]
@****************************************************
@* Set memory control registers *
@****************************************************
ldr r0,=SMRDATA @把memcfg.a中设定的总线参数写入到总线控制寄存器中
ldmia r0,{r1-r13} @读出总线参数到r1-r13中
ldr r0,=rBWSCON @总线控制寄存器基址
stmia r0,{r1-r13} @写入寄存器
@初始化cache,顺序:先关闭和清除,再配置禁止cache区,最后允许cache
@关闭cache
ldr r0,=rSYSCFG
ldr r1,=cache_0k
str r1,[r0]
@清除cache
ldr r0,=0x10002000
ldr r1,=0x10004800
mov r2,#0
flush:
str r2,[r0],#16
cmp r0,r1
bne flush
@配置禁止cache区
ldr r0,=rNCACHBE0
ldr r1,=0xc0000000
str r1,[r0]
ldr r0,=rNCACHBE1
ldr r1,=0xffffc800
str r1,[r0]
@打开cache
ldr r0,=rSYSCFG
ldr r1,=(en_wr_buf<<3)+(cache_cfg<<1)
str r1,[r0]
@;****************************************************
@;* Initialize stacks *
@;****************************************************
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 @ UndefMode
ldr sp,=Undef_stack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 @ AbortMode
ldr sp,=Abort_stack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 @ IRQMode
ldr sp,=IRQ_stack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 @ FIQMode
ldr sp,=FIQ_stack
orr r1,r0,#SVCMODE|NOINT
msr cpsr_cxsf,r1 @ SVCMode
ldr sp,=SVC_stack
orr r1,r0,#SYSMODE|NOINT
msr cpsr_cxsf,r1 @ userMode
ldr sp,=USR_stack
@ b . @发行版本，注释掉 db
bl load_preload @调试版本的bios，注释掉 db
mov pc,r0
.ltorg
SMRDATA:
@#*****************************************************************
@#* Memory configuration has to be optimized for best performance *
@#* The following parameter is not optimized. *
@#*****************************************************************
@#*** memory access cycle parameter strategy ***
@# 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
@# 2) The memory settings,here, are made the safe parameters even at 66Mhz.
@# 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
@# 4) DRAM refresh rate is for 40Mhz.
@#bank0 16bit BOOT ROM
@#bank1 8bit NandFlash
@#bank2 16bit IDE
@#bank3 8bit UDB
@#bank4 rtl8019
@#bank5 ext
@#bank6 16bit SDRAM
@#bank7 16bit SDRAM
.long 0x11444440
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) @ GCS0
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) @ GCS1
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) @ GCS2
.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) @ GCS3
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) @ GCS4
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) @ GCS5
.ifc "DRAM",BDRAMTYPE
.long ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN)) @ GCS6 check the MT value in parameter.a
.long ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN)) @ GCS7
.else
.long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) @ GCS6
.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @ GCS7
.endif
.long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) @ REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
.long 0x10 @ SCLK power down mode, BANKSIZE 32M/32M
.long 0x20 @ MRSR6 CL=2clk
.long 0x20 @ MRSR7
.end
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