📄 dat.h
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typedef struct Conf Conf;typedef struct FPsave FPsave;typedef struct ISAConf ISAConf;typedef struct Label Label;typedef struct Lock Lock;typedef struct MMU MMU;typedef struct Mach Mach;typedef struct Notsave Notsave;typedef struct PCArch PCArch;typedef struct Pcidev Pcidev;typedef struct PCMmap PCMmap;typedef struct Page Page;typedef struct PMMU PMMU;typedef struct Proc Proc;typedef struct Segdesc Segdesc;typedef struct Ureg Ureg;typedef struct Vctl Vctl;/* * parameters for sysproc.c */#define AOUT_MAGIC (I_MAGIC)struct Lock{ ulong key; ulong sr; ulong pc; Proc *p; ushort isilock;};struct Label{ ulong sp; ulong pc;};/* * FPsave.status */enum{ FPinit, FPactive, FPinactive,};struct FPsave{ ushort control; ushort r1; ushort status; ushort r2; ushort tag; ushort r3; ulong pc; ushort selector; ushort r4; ulong operand; ushort oselector; ushort r5; uchar regs[80]; /* floating point registers */};struct Conf{ ulong nmach; /* processors */ ulong nproc; /* processes */ ulong monitor; /* has monitor? */ ulong npage0; /* total physical pages of memory */ ulong npage1; /* total physical pages of memory */ ulong npage; /* total physical pages of memory */ ulong upages; /* user page pool */ ulong nimage; /* number of page cache image headers */ ulong nswap; /* number of swap pages */ int nswppo; /* max # of pageouts per segment pass */ ulong base0; /* base of bank 0 */ ulong base1; /* base of bank 1 */ ulong copymode; /* 0 is copy on write, 1 is copy on reference */ ulong ialloc; /* max interrupt time allocation in bytes */ ulong pipeqsize; /* size in bytes of pipe queues */};/* * MMU stuff in proc */#define NCOLOR 1struct PMMU{ Page* mmupdb; /* page directory base */ Page* mmufree; /* unused page table pages */ Page* mmuused; /* used page table pages */};/* * things saved in the Proc structure during a notify */struct Notsave{ ulong svflags; ulong svcs; ulong svss;};#include "../port/portdat.h"typedef struct { ulong link; /* link (old TSS selector) */ ulong esp0; /* privilege level 0 stack pointer */ ulong ss0; /* privilege level 0 stack selector */ ulong esp1; /* privilege level 1 stack pointer */ ulong ss1; /* privilege level 1 stack selector */ ulong esp2; /* privilege level 2 stack pointer */ ulong ss2; /* privilege level 2 stack selector */ ulong cr3; /* page directory base register */ ulong eip; /* instruction pointer */ ulong eflags; /* flags register */ ulong eax; /* general registers */ ulong ecx; ulong edx; ulong ebx; ulong esp; ulong ebp; ulong esi; ulong edi; ulong es; /* segment selectors */ ulong cs; ulong ss; ulong ds; ulong fs; ulong gs; ulong ldt; /* selector for task's LDT */ ulong iomap; /* I/O map base address + T-bit */} Tss;struct Segdesc{ ulong d0; ulong d1;};struct Mach{ int machno; /* physical id of processor */ ulong splpc; /* pc of last caller to splhi */ ulong* pdb; /* page directory base for this processor (va) */ Tss* tss; /* tss for this processor */ Segdesc gdt[6]; /* gdt for this processor */ Proc* proc; /* current process on this processor */ Proc* externup; /* extern register Proc *up */ Page* pdbpool; int pdbcnt; ulong ticks; /* of the clock since boot time */ Label sched; /* scheduler wakeup */ Lock alarmlock; /* access to alarm list */ void* alarm; /* alarms bound to this clock */ ulong fairness; /* for runproc */ int tlbfault; int tlbpurge; int pfault; int cs; int syscall; int load; int intr; vlong fastclock; /* last sampled value */ vlong intrts; /* time stamp of last interrupt */ int flushmmu; /* make current proc flush it's mmu state */ ulong spuriousintr; int lastintr; int loopconst; int cpumhz; int cpuhz; int cpuidax; int cpuiddx; char cpuidid[16]; char* cpuidtype; vlong mtrrcap; vlong mtrrdef; vlong mtrrfix[11]; vlong mtrrvar[32]; /* 256 max. */ int stack[1];};/* * Fake kmap */typedef void KMap;#define VA(k) ((ulong)(k))#define kmap(p) (KMap*)((p)->pa|KZERO)#define kunmap(k)struct{ Lock; int machs; /* bitmap of active CPUs */ int exiting; /* shutdown */ int ispanic; /* shutdown in response to a panic */}active;/* * routines for things outside the PC model, like power management */struct PCArch{ char* id; int (*ident)(void); /* this should be in the model */ void (*reset)(void); /* this should be in the model */ int (*serialpower)(int); /* 1 == on, 0 == off */ int (*modempower)(int); /* 1 == on, 0 == off */ void (*intrinit)(void); int (*intrenable)(Vctl*); void (*clockenable)(void); uvlong (*fastclock)(uvlong*);};/* * a parsed plan9.ini line */#define ISAOPTLEN 16#define NISAOPT 8struct ISAConf { char type[NAMELEN]; ulong port; ulong irq; ulong dma; ulong mem; ulong size; ulong freq; int nopt; char opt[NISAOPT][ISAOPTLEN];};extern PCArch *arch; /* PC architecture *//* * Each processor sees its own Mach structure at address MACHADDR. * However, the Mach structures must also be available via the per-processor * MMU information array machp, mainly for disambiguation and access to * the clock which is only maintained by the bootstrap processor (0). */Mach* machp[MAXMACH]; #define MACHP(n) (machp[n])extern Mach *m;#define up (((Mach*)MACHADDR)->externup)
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