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📄 4-schematic1-1.out

📁 无刷直流电动机的电子电路硬件设计后
💻 OUT
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**** 04/04/05 15:48:57 ********* PSpice 9.1 (Mar 1999) ******** ID# 0 ********

 ** circuit file for profile: 1 


 ****     CIRCUIT DESCRIPTION


******************************************************************************




** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT PROFILES

*Libraries: 
* Local Libraries :
.STMLIB ".\4.stl" 
* From [PSPICE NETLIST] section of pspice91.ini file:
.lib "nom.lib" 

*Analysis directives: 
.TRAN  0 1s 0 
.OPTIONS ABSTOL= 10.0p
.OPTIONS RELTOL= 0.1
.PROBE 
.INC "4-SCHEMATIC1.net" 


**** INCLUDING 4-SCHEMATIC1.net ****
* source 4
R_R5         N21990 VPH5  33  
D_D48         0 VPL5 MBR6035 
X_U6         VPL5 N48290 N48296 0 0 M_UN0001 N48349 M_UN0002 MAX913/MXM
E_E1         N21180 N19803 N20794 0 4
V_V3         VEC 0 -15Vdc
V_V4         N48296 0 15Vdc
V_V11         N21982 0  
+PULSE -2V 12V 16m 0.1n 0.1n 8m 24m
R_R6         N34652 N38778  33  
R_R1         N21180 N205220  33  
Z_Z7         VDC N205220 N19803 APT35G60BN
V_V7         N19272 0  
+PULSE -2V 12V 0.1n 0.1n 0.1n 0.1ms 0.2ms
X_U9A         N19272 N19339 N20761 $G_CD4000_VDD $G_CD4000_VSS CD4081B PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
Z_Z2         VDC VPH3 VPL3 APT45G100BN
D_D43         N19803 VDC MBR6035 
E_E3         N21990 VPL5 N21966 0 4
R_Rc         N39348 N28344  0.9  
V_V10         N21970 0  
+PULSE -2V 12V 0.1n 0.1n 0.1n 0.1ms 0.2ms
R_R7         N475491 N48290  1k  
V_V16         VCF 0 1.25Vdc
V_V17         N475491 0 -0.6Vdc
Z_Z3         VDC VPH5 VPL5 APT45G100BN
D_D44         VPL3 VDC MBR6035 
X_U2A         N21970 N21982 N22030 $G_CD4000_VDD $G_CD4000_VSS CD4081B PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_Ra         N47467 N28344  0.9  
Z_Z4         N19803 N372200 0 APT45G100BN
R_R3         N21858 VPH3  33  
R_Rb         N43028 N39291  0.9  
D_D45         VPL5 VDC MBR6035 
R_R9         N48349 0  100k  
V_V9         N21850 0  
+PULSE -2V 12V 8m 0.1n 0.1n 8m 24m
V_V12         N38620 0  
+PULSE -5V 15V 12m 0.1n 0.1n 8m 24m
V_V13         N34522 0  
+PULSE 15V -5V 4m 0.1n 0.1n 16m 24m
V_V14         N34652 0  
+PULSE -5V 15V 4m 0.1n 0.1n 8m 24m
D_D46         0 N19803 MBR6035 
E_DIFF2         N20794 0 VALUE {V(N20761,VCF)}
E_DIFF3         N21966 0 VALUE {V(N22030,VCF)}
R_R2         N34522 N33396  33  
E_DIFF1         N21834 0 VALUE {V(N21898,VCF)}
V_V8         N19339 0  
+PULSE -2V 12V 0.1n 0.1n 0.1n 8m 24m
E_E2         N21858 VPL3 N21834 0 4
V_V15         N21838 0  
+PULSE -2V 12V 0.1n 0.1n 0.1n 0.1ms 0.2ms
D_D47         0 VPL3 MBR6035 
Z_Z6         VPL5 N38778 0 APT45G100BN
V_V1         VDC 0 300Vdc
X_U1A         N21838 N21850 N21898 $G_CD4000_VDD $G_CD4000_VSS CD4081B PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
Z_Z5         VPL3 N33396 0 APT35G60BN
V_Eam         N19803 N42937  
+PULSE 20V -20V 8m 4m 4m 8m 24m
R_R4         N38620 N372200  33  
V_Ebm         VPL3 N43028  
+PULSE -20V 20V 4m 4m 4m 8m 24m
V_Ecm         VPL5 N39294  
+PULSE 20V -20V 0.1n 4m 4m 8m 24m
V_V2         VCC 0 15Vdc
L_L4         N42937 N47467  5mH  
L_L6         N39348 N39294  5mh  
L_L5         N39291 N28344  5mh  

**** RESUMING 4-schematic1-1.sim.cir ****
.INC "4-SCHEMATIC1.als"



**** INCLUDING 4-SCHEMATIC1.als ****
.ALIASES
R_R5            R5(1=N21990 2=VPH5 )
D_D48           D48(1=0 2=VPL5 )
X_U6            U6(+=VPL5 -=N48290 V+=N48296 V-=0 LE=0 GND=M_UN0001 Q=N48349
+  Qbar=M_UN0002 )
E_E1            E1(3=N21180 4=N19803 1=N20794 2=0 )
V_V3            V3(+=VEC -=0 )
V_V4            V4(+=N48296 -=0 )
V_V11           V11(+=N21982 -=0 )
R_R6            R6(1=N34652 2=N38778 )
R_R1            R1(1=N21180 2=N205220 )
Z_Z7            Z7(C=VDC G=N205220 E=N19803 )
V_V7            V7(+=N19272 -=0 )
X_U9A           U9A(A=N19272 B=N19339 J=N20761 VDD=$G_CD4000_VDD
+  VSS=$G_CD4000_VSS )
Z_Z2            Z2(C=VDC G=VPH3 E=VPL3 )
D_D43           D43(1=N19803 2=VDC )
E_E3            E3(3=N21990 4=VPL5 1=N21966 2=0 )
R_Rc            Rc(1=N39348 2=N28344 )
V_V10           V10(+=N21970 -=0 )
R_R7            R7(1=N475491 2=N48290 )
V_V16           V16(+=VCF -=0 )
V_V17           V17(+=N475491 -=0 )
Z_Z3            Z3(C=VDC G=VPH5 E=VPL5 )
D_D44           D44(1=VPL3 2=VDC )
X_U2A           U2A(A=N21970 B=N21982 J=N22030 VDD=$G_CD4000_VDD
+  VSS=$G_CD4000_VSS )
R_Ra            Ra(1=N47467 2=N28344 )
Z_Z4            Z4(C=N19803 G=N372200 E=0 )
R_R3            R3(1=N21858 2=VPH3 )
R_Rb            Rb(1=N43028 2=N39291 )
D_D45           D45(1=VPL5 2=VDC )
R_R9            R9(1=N48349 2=0 )
V_V9            V9(+=N21850 -=0 )
V_V12           V12(+=N38620 -=0 )
V_V13           V13(+=N34522 -=0 )
V_V14           V14(+=N34652 -=0 )
D_D46           D46(1=0 2=N19803 )
E_DIFF2          DIFF2(OUT=N20794 IN2=N20761 IN1=VCF )
E_DIFF3          DIFF3(OUT=N21966 IN2=N22030 IN1=VCF )
R_R2            R2(1=N34522 2=N33396 )
E_DIFF1          DIFF1(OUT=N21834 IN2=N21898 IN1=VCF )
V_V8            V8(+=N19339 -=0 )
E_E2            E2(3=N21858 4=VPL3 1=N21834 2=0 )
V_V15           V15(+=N21838 -=0 )
D_D47           D47(1=0 2=VPL3 )
Z_Z6            Z6(C=VPL5 G=N38778 E=0 )
V_V1            V1(+=VDC -=0 )
X_U1A           U1A(A=N21838 B=N21850 J=N21898 VDD=$G_CD4000_VDD
+  VSS=$G_CD4000_VSS )
Z_Z5            Z5(C=VPL3 G=N33396 E=0 )
V_Eam           Eam(+=N19803 -=N42937 )
R_R4            R4(1=N38620 2=N372200 )
V_Ebm           Ebm(+=VPL3 -=N43028 )
V_Ecm           Ecm(+=VPL5 -=N39294 )
V_V2            V2(+=VCC -=0 )
L_L4            L4(1=N42937 2=N47467 )
L_L6            L6(1=N39348 2=N39294 )
L_L5            L5(1=N39291 2=N28344 )
_    _(VCF=VCF)
_    _(VPH3=VPH3)
_    _(VPH5=VPH5)
_    _(VDC=VDC)
_    _(VPL3=VPL3)
_    _(VEC=VEC)
_    _(VCC=VCC)
_    _(VPL5=VPL5)
_    _(VCF=VCF)
_    _(VDC=VDC)
_    _(VPH3=VPH3)
_    _(VCC=VCC)
_    _(VPH5=VPH5)
_    _(VPL5=VPL5)
_    _(VPL3=VPL3)
_    _(VEC=VEC)
_    _(VSS=VSS)
_    _(VDD=VDD)
.ENDALIASES

**** RESUMING 4-schematic1-1.sim.cir ****
.END


**** Generated AtoD and DtoA Interfaces ****

*
* Analog/Digital interface for node N21982
*
* Moving X_U2A.U1:IN2 from analog node N21982 to new digital node N21982$AtoD
X$N21982_AtoD1
+ N21982
+ N21982$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface for node N19272
*
* Moving X_U9A.U1:IN1 from analog node N19272 to new digital node N19272$AtoD
X$N19272_AtoD1
+ N19272
+ N19272$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface for node N21970
*
* Moving X_U2A.U1:IN1 from analog node N21970 to new digital node N21970$AtoD
X$N21970_AtoD1
+ N21970
+ N21970$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface for node N21850
*
* Moving X_U1A.U1:IN2 from analog node N21850 to new digital node N21850$AtoD
X$N21850_AtoD1
+ N21850
+ N21850$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface for node N20761
*
* Moving X_U9A.U1:OUT1 from analog node N20761 to new digital node N20761$DtoA
X$N20761_DtoA1
+ N20761$DtoA
+ N20761
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ DtoA_4000B
+       PARAMS: DRVH=   1.4430E+03 DRVL=   1.4430E+03 CAPACITANCE=   0     
*
* Analog/Digital interface for node N22030
*
* Moving X_U2A.U1:OUT1 from analog node N22030 to new digital node N22030$DtoA
X$N22030_DtoA1
+ N22030$DtoA
+ N22030
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ DtoA_4000B
+       PARAMS: DRVH=   1.4430E+03 DRVL=   1.4430E+03 CAPACITANCE=   0     
*
* Analog/Digital interface for node N21898
*
* Moving X_U1A.U1:OUT1 from analog node N21898 to new digital node N21898$DtoA
X$N21898_DtoA1
+ N21898$DtoA
+ N21898
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ DtoA_4000B
+       PARAMS: DRVH=   1.4430E+03 DRVL=   1.4430E+03 CAPACITANCE=   0     
*
* Analog/Digital interface for node N19339
*
* Moving X_U9A.U1:IN2 from analog node N19339 to new digital node N19339$AtoD
X$N19339_AtoD1
+ N19339
+ N19339$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface for node N21838
*
* Moving X_U1A.U1:IN1 from analog node N21838 to new digital node N21838$AtoD
X$N21838_AtoD1
+ N21838
+ N21838$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B
+       PARAMS: CAPACITANCE=   0     
*
* Analog/Digital interface power supply subcircuits
*

X$CD4000_PWR 0 CD4000_PWR

**** 04/04/05 15:48:57 ********* PSpice 9.1 (Mar 1999) ******** ID# 0 ********

 ** circuit file for profile: 1 


 ****     Diode MODEL PARAMETERS


******************************************************************************




               MBR6035         X_U6.DX         X_U6.DP         X_U6.DX2        
          IS  792.900000E-09  800.000000E-18   10.000000E-15    1.000000E-15 
           N                                    1.000000E-03    1.000000E-03 
         ISR   21.960000E-06                                                 
         IKF    8.666                                                        
          RS    3.092000E-03                                                 
         CJO    4.498000E-09                                                 
          VJ     .75                                                         
           M     .478                                                        
         XTI    0                                                            


               D74CLMP         
          IS    1.000000E-15 
          RS    2            
         CJO    2.000000E-12 


**** 04/04/05 15:48:57 ********* PSpice 9.1 (Mar 1999) ******** ID# 0 ********

 ** circuit file for profile: 1 


 ****     BJT MODEL PARAMETERS


******************************************************************************




               X_U6.qin        X_U6.qmi        X_U6.qmo        X_U6.qoc        
               NPN             PNP             PNP             NPN             
          IS  800.000000E-18  800.000000E-18  800.000000E-18  800.000000E-18 
          BF   16.67            1.002000E+03    1.000000E+03  181            
          NF    1               1               1               1            
          BR    1               1               1               1            
          NR    1               1               1               1            
         CJC                                    1.000000E-15    1.000000E-15 
          TF                                                   15.800000E-12 
          TR                                    6.475000E-09    4.172000E-09 
          CN    2.42            2.2             2.2             2.42         
           D     .87             .52             .52             .87         


**** 04/04/05 15:48:57 ********* PSpice 9.1 (Mar 1999) ******** ID# 0 ********

 ** circuit file for profile: 1 


 ****     MOSFET MODEL PARAMETERS


******************************************************************************




               X_U6.PMOS       
               PMOS            
       LEVEL    1            
           L  100.000000E-06 
           W  100.000000E-06 
         VTO    0            
          KP   20.000000E-06 
       GAMMA    0            
         PHI     .6          
      LAMBDA    0            
          IS   10.000000E-15 
          JS    0            
          PB     .8          
        PBSW     .8          
          CJ    0            
        CJSW    0            

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