📄 int.s
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#---------------------------------------------------------------------------
# /* Invalidate BAT registers and flush MMU */
#---------------------------------------------------------------------------
bl INT_disable_invalidate_mmu
#---------------------------------------------------------------------------
# /* Enable MMU */
#---------------------------------------------------------------------------
bl INT_Enable_MMU
#---------------------------------------------------------------------------
# /* Flush data cache and disable data and instruction cache*/
#---------------------------------------------------------------------------
bl INT_flush_disable_cache
#---------------------------------------------------------------------------
# /* Diab data provides code for a ROM to RAM copy of initialized data
# upon startup as well as code to clear the BSS area. The following
# routine will verify a clearing of the BSS area but may be redundant
# if the Diab Data code is called. */
#---------------------------------------------------------------------------
#---------------------------------------------------------------------------
# /* Clear the BSS area */
#---------------------------------------------------------------------------
# addis r3,r0,__BSS_START@ha
# addi r3,r3,__BSS_START@l
# addis r4,r0,__BSS_END@ha
# addi r4,r4,__BSS_END@l
# addi r5,r0,0
#BSS_Loop:
# cmpl 0,r4,r3
# beq BSS_Loop_Done
# stw r5,0(r3)
# addi r3,r3,4
# b BSS_Loop
#BSS_Loop_Done:
#---------------------------------------------------------------------------
# /* Setup the vectors loaded flag to indicate to other routines in the
# system whether or not all of the default vectors have been loaded.
# If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
# Otherwise, if INT_Loaded_Flag is 0, registering an LISR causes the
# default vector to be loaded. We assume that Nucleus must co-exist
# with a target monitor, so INT_Loaded_Flag will be set to 0. If
# there is no target monitor to set up the vector table,
# INT_Loaded_Flag should be set to 1.
#---------------------------------------------------------------------------
addis r12,r0,INT_Loaded_Flag@ha # get upper 16 bits of address
li r11,0 # clear the r11 register
stw r11,INT_Loaded_Flag@l(r12) # store 0 to INT_Loaded_Flag
#---------------------------------------------------------------------------
# /* Setup initial stack pointer and small data base registers */
#---------------------------------------------------------------------------
lis r11,__SP_INIT@h
ori r1,r11,__SP_INIT@l
lis r13,_SDA_BASE_@h
ori r13,r13,_SDA_BASE_@l
lis r2,_SDA2_BASE_@h
ori r2,r2,_SDA2_BASE_@l
#---------------------------------------------------------------------------
# /* Initialize the system stack pointers. This is done after the BSS is
# clear because the TCD_System_Stack pointer is a BSS variable!. */
#---------------------------------------------------------------------------
lis r4,__BSS_END@h
ori r4,r4,__BSS_END@l # load end of BSS section
addi r1,r4,4 # move to next available space
addis r1,r1,SYSTEM_SIZE@ha # add in our system stack size
addi r1,r1,SYSTEM_SIZE@l
addi r4,r1,-8 # allocate space for EABI frame
#---------------------------------------------------------------------------
# /* Save the current System stack to TCD_System_Stack. */
#---------------------------------------------------------------------------
addis r10,r0,TCD_System_Stack@ha # get upper 16 bits and < 16 bits
stw r4,TCD_System_Stack@l(r10) # store the current stack
mr r14,r4 # save in preserved register
#---------------------------------------------------------------------------
# TMD_HISR_Stack_Ptr = (VOID *) current stack address;
#---------------------------------------------------------------------------
addi r4,r4,8 # move past system stack
addis r10,r0,TMD_HISR_Stack_Ptr@ha # get upper 16 bits and < 16 bits
stw r4,TMD_HISR_Stack_Ptr@l(r10) # store the current HISR stack
#---------------------------------------------------------------------------
# /* Store the max size of the Timer HISR stack to TMD_HISR_Stack_Size. */
# TMD_HISR_Stack_Size = TIMER_SIZE;
#---------------------------------------------------------------------------
li r9,TIMER_SIZE # load Timer HISR stack size
addis r10,r0,TMD_HISR_Stack_Size@ha # get upper 16 bits and < 16 bits
stw r9,TMD_HISR_Stack_Size@l(r10) # store the Timer HISR stack size
#---------------------------------------------------------------------------
# /* Store the current Timer HISR priority to TMD_HISR_Priority */
# TMD_HISR_Priority = TIMER_PRIORITY;
#---------------------------------------------------------------------------
li r8,TIMER_PRIORITY # get Timer HISR priority
addis r10,r0,TMD_HISR_Priority@ha # get upper 16 bits and < 16 bits
stw r8,TMD_HISR_Priority@l(r10) # store the Timer HISR priority
#---------------------------------------------------------------------------
# /* Add in the Timer HISR stack size to the current system stack size.
# /* Note: This current stack size will now be passed to the INC_Initialize
# routine as the first available memory location for allocating
# system memory blocks. This is why we store it into r3. */
#---------------------------------------------------------------------------
addi r1,r1,4 # move to next available
add r1,r1,r9
.if (TARGET_MONITOR==1)
#---------------------------------------------------------------------------
# /* Setup the vector table at address 0x0. Assuming the debugging
# environment includes a target monitor running on the development
# board, the default vector table will be at address 0xfff00000.
# Since Nucleus needs to steal some interrupts and the default vector
# table is in ROM or Flash memory, the vector table needs to be
# relocated to RAM. This is done by setting up a vector table at
# address 0x0 and clearing the IP bit in the MSR register. The table
# at address 0x0 will contain entries that branch to the corresponding
# entries of the table at address 0xfff00000. This will allow the
# target monitor to maintain its debugging functionality. When Nucleus
# needs to steal an interrupt, it will place its own vector table entry
# in the RAM copy of the table. This will prevent Nucleus from
# disrupting the operation of the target monitor.
#
# If your debugging environment does not use or setup the vector table,
# the code that sets up a vector table at address 0x0 should be
# removed. The code that clears the IP bit of the MSR register should
# be left alone. The vector table should be setup by locating the
# Nucleus vector table, INT_Vectors, to address 0x0. This can be
# accomplished by modifying the file demo.lnk.
#---------------------------------------------------------------------------
li r11,18 # load branch instruction opcode
li r12,26 # load # of bits to shift left
slw r11,r11,r12 # shift opcode to correct location
oris r11,r11,0x03f0 # setup LI field of branch instruction
li r12,0 # set r12 to point to RAM copy of vectors
INT_Vect_Setup_Loop:
stw r11,0(r12) # write new vector table entry
addi r12,r12,0x100 # point to next location in RAM vectors
cmpli 0,r12,0x1500 # check if we have reached end of vectors
bne INT_Vect_Setup_Loop # if not, go back to top of loop
.endif
.if (TARGET_MONITOR==1) | (STEAL_VECTS==1)
#---------------------------------------------------------------------------
# /* If a Target Monitor program is used or SDS should handle exceptions,
# then "steal" the minimum vectors that are needed for PLUS to operate.
# These are the Decrementer and External interrupts. All other interrupts
# in the vector table are untouched. NOTE: the Reset Vector (0x100) is
# not taken, thus if a reset is performed, PLUS will not be started. To
# run PLUS again, the image must be downloaded again as this will place
# the PC back at the _start symbol. */
#---------------------------------------------------------------------------
#---------------------------------------------------------------------------
# /* Steal the external interrupt */
#---------------------------------------------------------------------------
li r3,5 # external vector number
bl INT_Steal_Vector # call routine to steal vector
#---------------------------------------------------------------------------
# /* Steal the decrementer interrupt */
#---------------------------------------------------------------------------
li r3,9 # decrementer vector number
bl INT_Steal_Vector # call routine to steal vector
.endif
.if ENABLE_CACHE
#---------------------------------------------------------------------------
# /* Enable L1 and L2 data and instruction caches*/
#---------------------------------------------------------------------------
bl INT_enable_cache
.endif
#---------------------------------------------------------------------------
# /* Move the vector base to RAM at 0x0 */
#---------------------------------------------------------------------------
mfmsr r12 # get current MSR
rlwinm r12,r12,0,26,24 # clear IP bit
mtmsr r12 # write out new MSR
# /*************** Begin board specific code ***************/
bl wb_Init # initialize the WINBOND
# PCI-to-ISA bus bridge
bl sio_Init # Initialize the SuperI/O
# controller chip
# /*************** Begin board specific code ***************/
#---------------------------------------------------------------------------
# /* Load the DEC register with a value to create an interrupt
# to the kernel every 10ms. */
#---------------------------------------------------------------------------
lis r11,DEC_LOAD_UPPER
ori r11,r11,DEC_LOAD_LOWER
mtdec r11
#---------------------------------------------------------------------------
# /* Call INC_Initialize with a pointer to the first available memory
# address after the compiler's global data. This memory may be used
# by the application, for memory pool allocations, partitions, etc.
#---------------------------------------------------------------------------
addi r1,r1,4 # move to next available space
mr r3,r1
# mr r1,r4 # reset system stack to start
mr r1,r14 # reset system stack to start
b INC_Initialize
#}
#/*************************************************************************/
#/* */
#/* FUNCTION */
#/* */
#/* INT_Vectors_Loaded */
#/* */
#/* DESCRIPTION */
#/* */
#/* This function returns the flag that indicates whether or not */
#/* all the default vectors have been loaded. If it is false, */
#/* each LISR register also loads the ISR shell into the actual */
#/* vector table. */
#/* */
#/* CALLED BY */
#/* */
#/* TCC_Register_LISR Register LISR for vector */
#/* */
#/* CALLS */
#/* */
#/* None */
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