📄 int.s
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.skip 0x0500-(.-INT_Vectors) # External interrupt
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,5 # load vector number
ba INT_Shell
.skip 0x0600-(.-INT_Vectors) # Alignment error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,6 # load vector number
ba INT_Shell
.skip 0x0700-(.-INT_Vectors) # Program error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,7 # load vector number
ba INT_Shell
.skip 0x0800-(.-INT_Vectors) # Floating-point unavailable
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,8 # load vector number
ba INT_Shell
.skip 0x0900-(.-INT_Vectors) # Decrementer interrupt
ba INT_Timer_Interrupt
.skip 0x0C00-(.-INT_Vectors) # System call
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,26 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,12 # load vector number
ba INT_Shell
.skip 0x0D00-(.-INT_Vectors) # Trace
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,13 # load vector number
ba INT_Shell
.skip 0x1000-(.-INT_Vectors) # Instruction translation miss
.if NU_MMU_LITE > 0
mfspr r2, MMU_SPR_HASH1 # get first pointer
addi r1, 0, 8 # load 8 for counter
mfctr r0 # save counter
mfspr r3, MMU_SPR_ICMP # get first compare value
addi r2, r2, -8 # pre dec the pointer
im0:
mtctr r1 # load counter
im1:
lwzu r1, 8(r2) # get next pte
cmp MMU_C0, r1, r3 # see if found pte
bdnzf eq, im1 # dec count br if cmp ne and if count not zero
bne instrSecHash # if not found set up second hash or exit
lwz r1, +4(r2) # load tlb entry lower-word
andi. r3, r1, 8 # check G-bit
bne doISIp # if guarded, take an ISI
mtctr r0 # restore counter
mfspr r0, MMU_SPR_IMISS # get the miss address for the tlbli
mfspr r3, MMU_SRR1 # get the saved cr0 bits
mtcrf 0x80, r3 # restore CR0
mtspr MMU_RPA, r1 # set the pte
ori r1, r1, 0x100 # set reference bit
srw r1, r1, 8 # get byte 7 of pte
tlbli r0 # load the itlb
stb r1, +6(r2) # update page table
rfi # return to executing program
#
# Register usage:.5-46 MPC603e & EC603e RISC Microprocessors User's Manual MOTOROLA
# r0 is saved counter
# r1 is junk
# r2 is pointer to pteg
# r3 is current compare value
#
instrSecHash:
andi. r1, r3, 0x0040 # see if we have done second hash
bne doISI # if so, go to ISI exception
mfspr r2, MMU_SPR_HASH2 # get the second pointer
ori r3, r3, 0x0040 # change the compare value
addi r1, 0, 8 # load 8 for counter
addi r2, r2, -8 # pre dec for update on load
b im0 # try second hash
#+
# entry Not Found: synthesize an ISI exception
# guarded memory protection violation: synthesize an ISI exception
# Entry:
# r0 is saved counter
# r1 is junk
# r2 is pointer to pteg
# r3 is current compare value
#
doISIp:
mfspr r3, MMU_SRR1 # get MMU_SRR1
andi. r2,r3,0xffff # clean upper MMU_SRR1
addis r2, r2, 0x0800 # or in srr<4> = 1 to flag prot violation
b isi1:
doISI:
mfspr r3, MMU_SRR1 # get MMU_SRR1
andi. r2, r3, 0xffff # clean MMU_SRR1
addis r2, r2, 0x4000 # or in MMU_SRR1<1> = 1 to flag pte not found
mtctr r0 # restore counter
isi1: mtspr MMU_SRR1, r2 # set MMU_SRR1
mfmsr r0 # get msr
xori r0, r0, 0x8000 # flip the msr<tgpr> bit
mtcrf 0x80, r3 # restore CR0
mtmsr r0 # flip back to the native gprs
b ISI_Vector # go to instr. access exception
#
# /* End of NU_MMU_LITE conditional include for instruction TLB misses */
#
.else
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,16 # load vector number
ba INT_Shell
.endc
.skip 0x1100-(.-INT_Vectors) # Data load translation miss
.if NU_MMU_LITE > 0
mfspr r2, MMU_SPR_HASH1 # get first pointer
mtspr 272, r2
addi r1, 0, 8 # load 8 for counter
mtspr SPRG1, r1
mfctr r0 # save counter
mfspr r3, MMU_SPR_DCMP # get first compare value
mtspr SPRG3, r3
addi r2, r2, -8 # pre dec the pointer
dm0:
mtctr r1 # load counter
dm1:
lwzu r1, 8(r2) # get next pte
mtspr SPRG1, r1
cmp MMU_C0, r1, r3 # see if found pte
bdnzf eq, dm1 # dec count br if cmp ne and if count not zero
bne dataSecHash # if not found set up second hash or exit
lwz r1, +4(r2) # load tlb entry lower-word
mtspr SPRG1, r1
mtctr r0 # restore counter
mfspr r0, MMU_SPR_DMISS # get the miss address for the tlbld
mtspr SPRG0, r0
mfspr r3, MMU_SRR1 # get the saved cr0 bits
mtcrf 0x80, r3 # restore CR0
mtspr MMU_RPA, r1 # set the pte
ori r1, r1, 0x100 # set reference bit
srw r1, r1, 8 # get byte 7 of pte
tlbld r0 # load the dtlb
stb r1, +6(r2) # update page table
rfi # return to executing program
#+
# Register usage:
# r0 is saved counter
# r1 is junk
# r2 is pointer to pteg
# r3 is current compare value
#-
dataSecHash:
andi. r1, r3, 0x0040 # see if we have done second hash
bne doDSI # if so, go to DSI exception
mfspr r2, MMU_SPR_HASH2 # get the second pointer
ori r3, r3, 0x0040 # change the compare value
addi r1, 0, 8 # load 8 for counter
addi r2, r2, -8 # pre dec for update on load
b dm0 # try second hash
#
# /* End of NU_MMU_LITE conditional include for data TLB load misses */
#
.else
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,17 # load vector number
ba INT_Shell
.endc
.skip 0x1200-(.-INT_Vectors) # Data store translation miss
.if NU_MMU_LITE > 0
#+.5-48 MPC603e & EC603e RISC Microprocessors User's Manual MOTOROLA
# C=0 in dtlb and dtlb miss on store flow
# Entry:
# Vec = 1200
# MMU_SRR0 -> address of store that caused the exception
# MMU_SRR1 -> 0:3=cr0 4=lru way bit 5=1 16:31 = saved MSR
# msr<tgpr> -> 1
# MMU_SPR_DMISS -> ea that missed
# MMU_SPR_DCMP -> the compare value for the va that missed
# MMU_SPR_HASH1 -> pointer to first hash pteg
# MMU_SPR_HASH2 -> pointer to second hash pteg
#
# Register usage:
# r0 is saved counter
# r1 is junk
# r2 is pointer to pteg
# r3 is current compare value
#-.
tlbCeq0:
mfspr r2, MMU_SPR_HASH1 # get first pointer
addi r1, 0, 8 # load 8 for counter
mfctr r0 # save counter
mfspr r3, MMU_SPR_DCMP # get first compare value
addi r2, r2, -8 # pre dec the pointer
ceq0:
mtctr r1 # load counter
ceq1:
lwzu r1, 8(r2) # get next pte
cmp MMU_C0, r1, r3 # see if found pte
bdnzf eq, ceq1 # dec count br if cmp ne and if count not zero
bne cEq0SecHash # if not found set up second hash or exit
lwz r1, +4(r2) # load tlb entry lower-word
andi. r3,r1,0x80 # check the C-bit
beq cEq0ChkProt # if (C==0) go check protection modes
ceq2:
mtctr r0 # restore counter
mfspr r0, MMU_SPR_DMISS # get the miss address for the tlbld
mfspr r3, MMU_SRR1 # get the saved cr0 bits
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