📄 int.s
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#/*************************************************************************/
#/* */
#/* Copyright (c) 1993-2001 Accelerated Technology, Inc. */
#/* */
#/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
#/* subject matter of this material. All manufacturing, reproduction, */
#/* use, and sales rights pertaining to this subject matter are governed */
#/* by the license agreement. The recipient of this software implicitly */
#/* accepts the terms of the license. */
#/* */
#/*************************************************************************/
#/*************************************************************************/
#/*************************************************************************/
#/* */
#/* FILE NAME VERSION */
#/* */
#/* int.s Nucleus PLUS\MPC8245\Diab C/C++ 1.13.1 */
#/* */
#/* COMPONENT */
#/* */
#/* IN - Initialization */
#/* */
#/* DESCRIPTION */
#/* */
#/* This file contains the target processor dependent initialization */
#/* routines and data. */
#/* */
#/* */
#/* DATA STRUCTURES */
#/* */
#/* INT_Vectors Interrupt vector table */
#/* */
#/* FUNCTIONS */
#/* */
#/* INT_Initialize Target initialization */
#/* INT_Vectors_Loaded Returns a NU_TRUE if all the */
#/* default vectors are loaded */
#/* INT_Setup_Vector Sets up an actual vector */
#/* INT_disable_invalidate_mmu Invalidate BATs and flush MMU*/
#/* INT_Enable_MMU Enable MMU */
#/* INT_flush_disable_cache Flush data cache and disable */
#/* data and instruction cache */
#/* INT_enable_cache Enable cache */
#/* INT_Enable_Winbond Enables the Winbond chip PICs*/
#/* INT_Get_Iobase_Addr Allows access to IOBASE addr */
#/* */
#/* DEPENDENCIES */
#/* */
#/* nucleus.h System constants */
#/* */
#/* HISTORY */
#/* */
#/* NAME DATE REMARKS */
#/* */
#/* T. Weller 12\19\2001 Created inital version 1.13.1 */
#/* */
#/*************************************************************************/
.file "int.s"
#---------------------------------------------------------------------------
# /* Conditional Compilation Switches. */
#---------------------------------------------------------------------------
ENABLE_CACHE .equ 0 # Enable cache use
NU_MMU_LITE .equ 1 # Enable limited MMU use and Interrupt Handling
BOOT_FROM_FLASH .equ 0 # Enable initialization for execution from FLASH
TARGET_MONITOR .equ 0 # Map 0x0 vector table to 0xfff0 vector table
STEAL_VECTS .equ 0 # Setup minimal vector table entries
.if NU_MMU_LITE > 0
#
# /* Include definitions for MMU services */
#
MMU_SPR_DMISS .equ 976 #1010
MMU_SPR_DCMP .equ 977 #1011
MMU_SPR_HASH1 .equ 978 #1012
MMU_SPR_HASH2 .equ 979 #1013
MMU_SPR_IMISS .equ 980 #1014
MMU_SPR_ICMP .equ 981 #1015
MMU_RPA .equ 982
MMU_C0 .equ 0
MMU_DAR .equ 19
MMU_DSISR .equ 18
MMU_SRR0 .equ 26
MMU_SRR1 .equ 27
EXC_R0 .equ r9
EXC_R1 .equ r10
EXC_R2 .equ r11
EXC_R3 .equ r12
.endc
#
# Define constants used in low-level initialization.
#
LOCKOUT .equ 0x0000 # Interrupt lockout value
LOCK_MSK .equ 0x8000 # Interrupt lockout mask value
MSR_RI_MSK .equ 0x0002 # MSR[RI] mask
STATE_MASK .equ 0x4000 # Processor State Mask
SUP_STATE .equ 0x4000 # Supervisor State MSR [PR]
SYSTEM_SIZE .equ 1032 # Define the system stack size
# plus 8 extra bytes for DIAB/DATA
# stack frame.
TIMER_SIZE .equ 1032 # Define timer HISR stack size
# plus 8 extra bytes for DIAB/DATA
# stack frame.
TIMER_PRIORITY .equ 2 # Timer HISR priority (values from
# 0 to 2, where 0 is highest)
#
# HID0 definitions for MPC8245.
#
HID0 .equ 0x3f0 # HID0 Special Purpose Register
H0_ICFI .equ 0x0800 # HID0 I-Cache Flash Invalidate
H0_DCFI .equ 0x0400 # HID0 D-Cache Flash Invalidate
H0_ICE .equ 0x8000 # HID0 I-Cache Enable
H0_DCE .equ 0x4000 # HID0 D-Cache Enable
H0_ILOCK .equ 0x2000 # HID0 I-Cache Lock
H0_DLOCK .equ 0x1000 # HID0 D-Cache Lock
NUM_SETS .equ 128 # sets in the 8245 cache
NUM_WAYS .equ 4 # blocks per set in the 8245
BLOCK_SIZE .equ 32 # size of a block in the 8245
# ** Begin board specific code **
#
# Sandpoint board definitions from Motorola.
#
# The IOBase address is 0x80000000 for Map A (PREP).
# The IOBase address is 0xFE000000 for Map B (CHRP).
# PREP_IO_BASE .equ 0x8000 # upper 16 bits addr. of IO_BASE in PREP
CHRP_IO_BASE .equ 0xfe00 # upper 16 bits addr. of IO_BASE in CHRP
# SET IOBASE_ADDR according to the map used for your Sanpoint
# IOBASE_ADDR .equ PREP_IO_BASE # This uses MAP A - PREP
IOBASE_ADDR .equ CHRP_IO_BASE # This uses MAP B - CHRP
# ** Begin board specific code **
# In the MPC8240 the DEC reg is decremented at the bus clock rate/4
# (66mhz/4) or once every 0.0606us. When 0x28488(165000D)is loaded into
# the DEC register, the decrementer interrupt will occur in 10ms.
DEC_LOAD_UPPER .equ 0x0002 #
DEC_LOAD_LOWER .equ 0x8488 #
#/* End of low-level initialization constants. */
#
# Global allocations for this file
#
.align 2
.data
#
#/* Define the initialization flag that indicates whether or not all of the
# default vectors have been loaded during initialization. */
#
#INT INT_Loaded_Flag;
#
.comm INT_Loaded_Flag,4
#
# /* Define the global task control thread pointer */
#
# extern UNSIGNED *TCD_Current_Thread;
#
#/* Define the global system stack variable. This is setup by the
# initialization routine. */
#
#extern VOID *TCD_System_Stack;
#
#/* Define the global data structures that need to be initialized by this
# routine. These structures are used to define the system timer management
# HISR. */
#
#extern VOID *TMD_HISR_Stack_Ptr;
#extern UNSIGNED TMD_HISR_Stack_Size;
#extern INT TMD_HISR_Priority;
#
#/* Define extern function references. */
#
#VOID INC_Initialize(VOID *first_available_memory);
#VOID TCT_Interrupt_Context_Save(VOID);
#VOID TCT_Interrupt_Context_Restore(VOID);
#VOID TCC_Dispatch_LISR(INT vector_number);
#VOID TMT_Timer_Interrupt(void);
#
.globl INT_Initialize, main, __init_main, TCT_Interrupt_Context_Save
.globl TCT_Interrupt_Context_Restore, TCC_Dispatch_LISR
.globl TMT_Timer_Interrupt, INT_Vectors
.globl INT_Timer_Interrupt, exit, nucleus_main, _start
#
# /* Define the default Nucleus vector table for the 60x. Note that any LISRs
# registered with Nucleus will not be able to manipulate the SRR0 register.
# So if the interrupt condition requires that the point of interrupt return
# be modified, that should be done here before it is saved on the stack.
# The SRR0 value saved here is the location to which Nucleus will return
# from interrupt */
#
# /* If either use of Target Monitor software which maintains a vector
# table at 0xfff00000 or use of SDS debugger exception trapping is
# desired, then locate the INT_Vectors structure in the .text section,
# otherwise locate it in the .vectors section which will is defined in
# the linker file. */
.if (TARGET_MONITOR==1) | (STEAL_VECTS==1)
.section ".text",,x
.else
.section ".vectors",,x
.endif
.align 2
.globl INT_Vectors
INT_Vectors:
.skip 0x0100-(.-INT_Vectors) # System reset
_start:
lis r3,INT_Initialize@h
ori r3,r3,INT_Initialize@l # Load start address
mtspr CTR,r3
bctr # Jump to INT_Initialize
.skip 0x0200-(.-INT_Vectors) # Machine check
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,2 # load vector number
ba INT_Shell
.skip 0x0300-(.-INT_Vectors) # Data access error
.globl DSI_Vector
DSI_Vector:
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,3 # load vector number
ba INT_Shell
.skip 0x0400-(.-INT_Vectors) # Instruction access error
.globl ISI_Vector
ISI_Vector:
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,4 # load vector number
ba INT_Shell
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