📄 winbond.c
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/************************************************************************/
/* */
/* Copyright (c) 2001 by Accelerated Technology, Inc. */
/* */
/* PROPRIETARY RIGHTS of Accelerated Technology are involved in */
/* the subject matter of this material. All manufacturing, */
/* reproduction, use, and sales rights pertaining to this subject */
/* matter are governed by the license agreement. The recipient of */
/* this software implicitly accepts the terms of the license. */
/* */
/* */
/************************************************************************/
/************************************************************************/
/* FILE NAME VERSION */
/* */
/* winbond.c Nucleus PLUS\MPC8245\Diab C/C++ 1.13.1 */
/* */
/* */
/* DESCRIPTION */
/* */
/* Support services for the Winbond W83C553F System I/O */
/* controller with PCI Arbiter. */
/* */
/* */
/* DATA STRUCTURES */
/* */
/* none */
/* */
/* FUNCTIONS */
/* */
/* wb_Init */
/* */
/* DEPENDENCIES */
/* NA */
/* */
/* HISTORY */
/* */
/* NAME DATE REMARKS */
/* */
/* T. Weller 12\19\2001 Created inital version 1.13.1 */
/************************************************************************/
#include "winbond.h"
/************************************************************************/
/* wb_Init */
/* */
/* */
/* DESCRIPTION */
/* */
/* Performs initialization of the Winbond controller. */
/* */
/************************************************************************/
STATUS wb_Init()
{
/* Assume success */
STATUS status = NU_SUCCESS;
UINT8 tByte;
/* Configure the cascaded interrupt controllers */
/* Select ICW1, ICW4 write needed */
WB_OUTBYTE( IO_Base + PIC1_ICW1, 0x11 );
/* Set address of interrupt vector */
WB_OUTBYTE( IO_Base + PIC1_ICW2, 0x00 );
/* Slave IC is cascaded on IRQ 2*/
WB_OUTBYTE( IO_Base + PIC1_ICW3, 0x04 );
/* Single bit interrupt sequence mode */
WB_OUTBYTE( IO_Base + PIC1_ICW4, 0x01 );
/* Lock out all but slave interrupt controller */
WB_OUTBYTE( IO_Base + PIC1_OCW1, 0xfb );
/* Select ICW1, ICW4 write needed */
WB_OUTBYTE( IO_Base + PIC2_ICW1, 0x11 );
/* Set address of interrupt vector */
WB_OUTBYTE( IO_Base + PIC2_ICW2, 0x08 );
/* Set slave ID */
WB_OUTBYTE( IO_Base + PIC2_ICW3, 0x02 );
/* Single bit interrupt sequence mode */
WB_OUTBYTE( IO_Base + PIC2_ICW4, 0x01 );
/* Lock out all interrupts on slave interrupt controller */
WB_OUTBYTE( IO_Base + PIC2_OCW1, 0xff );
/* End of interrupt controller configuration */
WB_OUTBYTE( IO_Base + PIC1_OCW1, 0xe7 );
tByte = WB_INBYTE( IO_Base + PIC1_INT_CONTROL);
tByte = 0x00; /* All channels set to edge triggered */
WB_OUTBYTE( IO_Base + PIC1_INT_CONTROL, tByte);
WB_OUTBYTE( IO_Base + PIC2_INT_CONTROL, tByte);
return status;
}
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