📄 int_ads.s
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stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,13 # load vector number
ba INT_Shell
.skip 0x1000-(.-INT_Vectors) # Software emulation
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,16 # load vector number
ba INT_Shell
.skip 0x1100-(.-INT_Vectors) # Instruction TLB miss
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,17 # load vector number
ba INT_Shell
.skip 0x1200-(.-INT_Vectors) # Data TLB miss
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,18 # load vector number
ba INT_Shell
.skip 0x1300-(.-INT_Vectors) # Instruction TLB error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,19 # load vector number
ba INT_Shell
.skip 0x1400-(.-INT_Vectors) # Data TLB error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,20 # load vector number
ba INT_Shell
.skip 0x1C00-(.-INT_Vectors) # Data breakpoint
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,28 # load vector number
ba INT_Shell
.skip 0x1D00-(.-INT_Vectors) # Instruction breakpoint
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,29 # load vector number
ba INT_Shell
.skip 0x1E00-(.-INT_Vectors) # Peripheral breakpoint
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,30 # load vector number
ba INT_Shell
.skip 0x1F00-(.-INT_Vectors) # Non-maskable development port
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,31 # load vector number
ba INT_Shell
#
#/*************************************************************************/
#/* */
#/* FUNCTION */
#/* */
#/* INT_Initialize */
#/* */
#/* DESCRIPTION */
#/* */
#/* This function sets up the global system stack variable and */
#/* transfers control to the target independent initialization */
#/* function INC_Initialize. Responsibilities of this function */
#/* include the following: */
#/* */
#/* - Setup necessary processor/system control registers */
#/* - Initialize the vector table */
#/* - Setup the system stack pointers */
#/* - Setup the timer interrupt */
#/* - Calculate the timer HISR stack and priority */
#/* - Calculate the first available memory address */
#/* - Transfer control to INC_Initialize to initialize all of */
#/* the system components. */
#/* */
#/* AUTHOR */
#/* */
#/* Barry Sellew, Accelerated Technology, Inc. */
#/* */
#/* CALLED BY */
#/* */
#/* __init_main ENTRY routine in crt0.s which*/
#/* is supplied by DIABDATA. */
#/* */
#/* CALLS */
#/* */
#/* INC_Initialize Common initialization */
#/* */
#/* INPUTS */
#/* */
#/* None */
#/* */
#/* OUTPUTS */
#/* */
#/* None */
#/* */
#/* HISTORY */
#/* */
#/* NAME DATE REMARKS */
#/* */
#/* Barry Sellew 06-24-1996 Created initial version 1.0 */
#/* */
#/*************************************************************************/
#VOID INT_Initialize(void)
#{
.text
.align 2
INT_Initialize:
main:
__init_main: # global label for DIABDAT crt0.s
#
# /* Disable data cache */
#
lis r3,CACHE_DISABLE
mtspr DC_CST,r3
#
# /* Enable machine check exceptions and set RI bit */
#
mfmsr r3
ori r3,r3,0x1002
mtmsr r3
#
# /* Set ICTRL = 7 to turn off show cycles */
#
lis r3,0x0000
ori r3,r3,0x0007
mtspr ICTRL,r3
#
# /* Set base address of internal memory-mapped registers */
#
lis r4,0x0220
ori r4,r4,0x0000
mtspr IMMR,r4
#
# /* SIUMCR |= 0x00032600 */
#
lwz r3,SIUMCR(r4)
oris r3,r3,0x0003
ori r3,r3,0x2640
stw r3,SIUMCR(r4)
#
# /* Enable bus monitor, disable SWT */
#
lis r3,0xffff
ori r3,r3,0xff88
stw r3,SYPCR(r4)
#
# /* Enable decrementer and halt it when FREEZE is asserted */
#
li r3,0x00c3
sth r3,TBSCR(r4)
#
# /* Unlock Real-time clock control register */
#
lis r3,0x55cc
ori r3,r3,0xaa33
stw r3,RTCSCK(r4)
#
# /* Disable real-time clock */
#
li r3,0x00c2
sth r3,RTCSC(r4)
#
# /* Disable periodic timer */
#
li r3,0x0082
sth r3,PISCR(r4)
#
# /* Setup memory controller registers */
#
lis r3,0xffe0 # Flash at 0xffe00000
ori r3,r3,0x0954
stw r3,OR0(r4)
lis r3,0xffe0
ori r3,r3,0x0001
stw r3,BR0(r4)
lis r3,0xffff # BCSR at 0xf0000000
ori r3,r3,0x8110
stw r3,OR1(r4)
lis r3,0xf000
ori r3,r3,0x0001
stw r3,BR1(r4)
lis r3,0xfe00 # DRAM at 0x0
ori r3,r3,0x0800
stw r3,OR2(r4)
lis r3,0x0000
ori r3,r3,0x0081
stw r3,BR2(r4)
li r3,0x0800 # MPTPR = 0x0800 (16bit register)
sth r3,MPTPR(r4)
lis r3,0xc0a2 # MAMR = 0xc0a21114
ori r3,r3,0x1114
stw r3,MAMR(r4)
addis r5,r0,INT_UPM_Table@ha # Get beginning address of UPM table
addi r5,r5,INT_UPM_Table@l
addi r6,r5,256 # Get end address of UPM table
lis r7,0x0080 # Load command: write,UPM,MAD=0
INT_UPM_Loop:
lwz r3,0(r5) # Get table entry
stw r3,MDR(r4) # Copy to MDR
stw r7,MCR(r4) # Issue command to MCR
addi r5,r5,4 # Point to next entry in table
addi r7,r7,1 # Increment MAD field of MCR command
cmp r5,r6 # Finished?
blt INT_UPM_Loop # If not, keep looping
#
# /* Clear the BSS area */
#
addis r3,r0,__BSS_START@ha
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