📄 int_est.s
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#/*************************************************************************/
#/* */
#/* Copyright (c) 1993-1995 Accelerated Technology, Inc. */
#/* */
#/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
#/* subject matter of this material. All manufacturing, reproduction, */
#/* use, and sales rights pertaining to this subject matter are governed */
#/* by the license agreement. The recipient of this software implicitly */
#/* accepts the terms of the license. */
#/* */
#/*************************************************************************/
#
#/*************************************************************************/
#/* */
#/* FILE NAME VERSION */
#/* */
#/* int_est.s PLUS/MPC860/D 1.3 */
#/* */
#/* COMPONENT */
#/* */
#/* IN - Initialization */
#/* */
#/* DESCRIPTION */
#/* */
#/* This file contains the target processor dependent initialization */
#/* routines and data. */
#/* */
#/* AUTHOR */
#/* */
#/* Barry Sellew, Accelerated Technology, Inc. */
#/* */
#/* DATA STRUCTURES */
#/* */
#/* INT_Vectors Interrupt vector table */
#/* */
#/* FUNCTIONS */
#/* */
#/* INT_Initialize Target initialization */
#/* INT_Vectors_Loaded Returns a NU_TRUE if all the */
#/* default vectors are loaded */
#/* INT_Setup_Vector Sets up an actual vector */
#/* */
#/* DEPENDENCIES */
#/* */
#/* nucleus.h System constants */
#/* */
#/* HISTORY */
#/* */
#/* NAME DATE REMARKS */
#/* */
#/* Barry Sellew 06-24-1996 Created initial version 1.0 */
#/* Barry Sellew 06-16-1997 Added MMU, cache, and board */
#/* initialization and added support */
#/* for SIU, CPM, and LISRs, ver. 1.1*/
#/* Barry Sellew 06-16-1997 Verified version 1.1 */
#/* Barry Sellew 09-10-1997 Created and verified version 1.2 */
#/* Barry Sellew 02-02-1998 Created and verified version 1.3 */
#/* */
#/*************************************************************************/
.file "int.s"
##define NU_SOURCE_FILE
#
##include "nucleus.h" /* System constants */
#
#
#/* Define constants used in low-level initialization. */
#
#
DEC_LOAD .equ 0x3d09 # DEC load value (25MHz/16 / 100)
LOCKOUT .equ 0x0000 # Interrupt lockout value
LOCK_MSK .equ 0x8000 # Interrupt lockout mask value
STATE_MASK .equ 0x4000 # Processor State Mask
SUP_STATE .equ 0x4000 # Supervisor State MSR [PR]
IRQ_STACK_SIZE .equ 136 # Number of bytes in IRQ stack
# Note that the IRQ interrupt,
# by default, is managed by
# Nucleus PLUS. Only several
# words are actually used. The
# system stack is what will
# actually be used for Nuclues
# PLUS managed IRQ interrupts.
# Plus 8 extra bytes for the
# DIAB/DATA stack frame.
SYSTEM_SIZE .equ 1032 # Define the system stack size
# plus 8 extra bytes for the
# DIAB/DATA stack frame.
TIMER_SIZE .equ 1032 # Define timer HISR stack size
# plus 8 extra bytes for the
# DIAB/DATA stack frame.
TIMER_PRIORITY .equ 2 # Timer HISR priority (values from
# 0 to 2, where 0 is highest)
CACHE_DISABLE .equ 0x0400 # Command to disable cache
CACHE_ENABLE .equ 0x0200 # Command to enable cache
CACHE_UNLK_ALL .equ 0x0a00 # Command to unlock all cache entries
CACHE_INV_ALL .equ 0x0c00 # Command to invalidate all entries
#
#/* Define offsets of memory-mapped registers. All of these are offset
# from the base address contained in the IMMR register
#
SIUMCR .equ 0x000 # SIU Module Control Register
SYPCR .equ 0x004 # SIU System Protection Control
SIVEC .equ 0x01c # SIU Interrupt Vector
BR0 .equ 0x100 # Base Register 0
OR0 .equ 0x104 # Option Register 0
BR1 .equ 0x108 # Base Register 1
OR1 .equ 0x10C # Option Register 1
BR2 .equ 0x110 # Base Register 2
OR2 .equ 0x114 # Option Register 2
BR3 .equ 0x118 # Base Register 3
OR3 .equ 0x11C # Option Register 3
BR4 .equ 0x120 # Base Register 4
OR4 .equ 0x124 # Option Register 4
BR5 .equ 0x128 # Base Register 5
OR5 .equ 0x12C # Option Register 5
BR6 .equ 0x130 # Base Register 6
OR6 .equ 0x134 # Option Register 6
BR7 .equ 0x138 # Base Register 7
OR7 .equ 0x13C # Option Register 7
MCR .equ 0x168 # Memory Command
MAMR .equ 0x170 # Machine A Mode Register
MBMR .equ 0x174 # Machine B Mode Register
MPTPR .equ 0x17A # Memory Periodic Timer Prescaler
MDR .equ 0x17C # Memory Data
TBSCR .equ 0x200 # Time Base Status and Control Register
RTCSC .equ 0x220 # Real Timer Clock Status and Control
PISCR .equ 0x240 # PIT Status and Control
RTCSCK .equ 0x320 # Real-time Clock Status Control Key
CIVR .equ 0x930 # CP Interrupt Vector Register
CICR .equ 0x940 # CP Interrupt Configuration Register
CISR .equ 0x94C # CP In-Service Register
#
#/* End of low-level initialization constants. */
#
#
# Global Allocations for module this file
#
.align 2
.data
#
#/* Define the initialization flag that indicates whether or not all of the
# default vectors have been loaded during initialization. */
#
#INT INT_Loaded_Flag;
#
.comm INT_Loaded_Flag,4
#
# /* Define the global task control thread pointer */
#
# extern UNSIGNED *TCD_Current_Thread;
#
#/* Define the global system stack variable. This is setup by the
# initialization routine. */
#
#extern VOID *TCD_System_Stack;
#
#/* Define the global data structures that need to be initialized by this
# routine. These structures are used to define the system timer management
# HISR. */
#
#extern VOID *TMD_HISR_Stack_Ptr;
#extern UNSIGNED TMD_HISR_Stack_Size;
#extern INT TMD_HISR_Priority;
#
#/* Define extern function references. */
#
#VOID INC_Initialize(VOID *first_available_memory);
#VOID TCT_Interrupt_Context_Save(VOID);
#VOID TCT_Interrupt_Context_Restore(VOID);
#VOID TCC_Dispatch_LISR(INT vector_number);
#VOID TMT_Timer_Interrupt(void);
#
.globl INT_Initialize, main, __init_main, TCT_Interrupt_Context_Save
.globl TCT_Interrupt_Context_Restore, TCC_Dispatch_LISR
.globl TMT_Timer_Interrupt, INT_Timer_Interrupt, exit
#
# /* Define the UPM_A table to be used for DRAM programming */
#
INT_UPMA_Table:
.long 0xffffff24, 0x0ff3cc24, 0x0ff3cc04, 0x0cf3cc04
.long 0x00f3cc04, 0x00f3cc00, 0x37f7cc47, 0x00000000
.long 0xfffeff24, 0x0ff3cc24, 0x0ff3cc04, 0x08f3cc04
.long 0x00f3cc00, 0x00f3cc0c, 0x0cf3cc44, 0x00f3ec08
.long 0x03f3ec04, 0x00f3ec40, 0x00f3cc0c, 0x0cf3cc44
.long 0x00f3ec00, 0x00f3ec04, 0x3ff7ec47, 0x00000000
.long 0xffffff24, 0x0fafcc24, 0x0fafcc04, 0x08afcc04
.long 0x00afcc00, 0x37ffcc47, 0x00000000, 0x00000000
.long 0xffffff24, 0x0fafcc24, 0x0fafcc04, 0x08afcc00
.long 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00
.long 0x07afcc4c, 0x08afcc00, 0x372fcc47, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04
.long 0x7fffcc04, 0xffffcc86, 0xffffcc05, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
#
# /* Define the UPM_B table to be used for SRAM programming */
#
INT_UPMB_Table:
.long 0x0ff3fc00, 0x1ff7fc07, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x0ff3fc00, 0x0ff3fc08, 0x0ff3fc08, 0x0ff3fc08
.long 0x0ff3fc08, 0x1ff7fc07, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x0cfffc00, 0x13fffc07, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x0ffffc00, 0x01fffc08, 0x01fffc08, 0x01fffc08
.long 0x01fffc07, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
.long 0x00000000, 0x00000000, 0x00000000, 0x00000000
#
# /* Define the default Nucleus vector table for the 860. Note that any LISRs
# registered with Nucleus will not be able to manipulate the SRR0 register.
# So if the interrupt condition requires that the point of interrupt return
# be modified, that should be done here before it is saved on the stack.
# The SRR0 value saved here is the location to which Nucleus will return
# from interrupt */
#
#
.section ".vectors",,x
.align 2
INT_Vectors:
.skip 0x0100-(.-INT_Vectors) # System reset
ba INT_Initialize
.skip 0x0200-(.-INT_Vectors) # Machine check
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,2 # load vector number
ba INT_Shell
.skip 0x0500-(.-INT_Vectors) # External interrupt
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,5 # load vector number
ba INT_Shell
.skip 0x0600-(.-INT_Vectors) # Alignment error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,6 # load vector number
ba INT_Shell
.skip 0x0700-(.-INT_Vectors) # Program error
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,7 # load vector number
ba INT_Shell
.skip 0x0900-(.-INT_Vectors) # Decrementer interrupt
ba INT_Timer_Interrupt
.skip 0x0C00-(.-INT_Vectors) # System call
addi r1,r1,-8 # subtract 8 bytes for DIAB/DATA
stw r12,0(r1) # save r12
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