📄 pquicc.c
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status = NU_Allocate_Memory (&System_Memory, &pointer, 2000, NU_NO_SUSPEND);
if (status != NU_SUCCESS)
while(1);
/* pointer = normalize_ptr(pointer); */
status = NU_Create_HISR (&PQUICC_Ether_Inter_Control, "ETHRHISR",
PQUICC_Recv_HISR, 0, pointer, 2000);
if (status != NU_SUCCESS)
while(1);
/* get the addresses of internal registers */
immr = get_IMMR() & 0xffff0000; /* Internal Memory Mapping Register */
pquicc = (PDA *)(get_IMMR() & 0xffff0000 + 0x940);
/* Step 1-35 are listed in 16.14.24.23 SCC Ethernet example of MPC860 UM. */
/*** General initialization of QUICC and SCC's ***/
#ifdef MBX
pquicc->pio_papar |= ((1<<1)|(1<<0));
pquicc->pio_padir &= ~((1<<1)|(1<<0));
pquicc->pio_paodr &= ~((1<<1)|(1<<0));
pquicc->pio_pcpar &= ~((1<<5)|(1<<4));
pquicc->pio_pcdir &= ~((1<<5)|(1<<4));
pquicc->pio_pcso |= ((1<<5)|(1<<4));
pquicc->pio_papar |= ((1<<11)|(1<<9));
pquicc->pio_padir &= ~((1<<11)|(1<<9));
pquicc->si_sicr &= ~0xffffff00;
pquicc->si_sicr |= 0x2c;
pquicc->si_sicr &= ~((7<<3)|(7<<0));
pquicc->si_sicr |= ((7<<3)|(5<<0));
pquicc->si_sicr &= ~((1<<6));
#endif /*MBX*/
#ifdef ADS
/* Step 1: PA14=ETHTX, PA15=ETHRX */
pquicc->pio_papar |= (0x0003);
pquicc->pio_padir &= ~(0x0003);
pquicc->pio_paodr &= ~(0x0002);
/* Step 2: PC10/CD1=RENA, PC11/CTS1=CLSN */
pquicc->pio_pcpar &= ~(0x0030);
pquicc->pio_pcdir &= ~(0x0030);
pquicc->pio_pcso |= 0x0030;
/* Step 3: don't enable TENA now. */
/* Step 4: PA6=ETHTCK, PA7=ETHRCK */
pquicc->pio_papar |= (0x0300);
pquicc->pio_padir &= ~(0x0300);
/* Step 5: CLK1 and CLK2 pins to SCC1 using the SI. Write the R1CS bits
SICR to 101 and T1CS to 100. si clock route: CLK1-TCLK, CLK2-RCLK */
/* Step 6: Connect SCC1 to NMSI and clear SC1 bit in SICR. */
pquicc->si_sicr &= ~0xffffff00;
pquicc->si_sicr |= 0x2c;
#endif /* ADS */
#ifdef EST
/* Step 1: PA14=ETHTX, PA15=ETHRX */
pquicc->pio_papar |= (0x0003);
pquicc->pio_padir &= ~(0x0003);
pquicc->pio_paodr &= ~(0x0002);
/* Step 2: PC10/CD1=RENA, PC11/CTS1=CLSN */
pquicc->pio_pcpar &= ~(0x0030);
pquicc->pio_pcdir &= ~(0x0030);
pquicc->pio_pcso |= 0x0030;
/* Step 3: don't enable TENA now. */
/* Step 4: PA6=ETHTCK, PA7=ETHRCK */
pquicc->pio_papar |= (0x0300);
pquicc->pio_padir &= ~(0x0300);
/* Step 5: CLK1 and CLK2 pins to SCC1 using the SI. Write the R1CS bits
SICR to 101 and T1CS to 100. si clock route: CLK1-TCLK, CLK2-RCLK */
/* Step 6: Connect SCC1 to NMSI and clear SC1 bit in SICR. */
pquicc->si_sicr &= ~0xffffff00;
pquicc->si_sicr |= 0x2c;
#endif /* EST */
/* Step 7: Initialize SDCR of SDMA to 0x1. */
*((unsigned long *) (immr + 0x30)) = 0x1;
/*** INITIALIZE ETHERNET SPECIFIC PROTOCOL PARAMATER RAM ***/
/* Step 25, 26: Initialize the RX BD and TX BD rings. */
PQUICC_BD_Init(10);
/* Step 8: Write RBASE & TBASE in the SCC parameter RAM. */
/*pquicc->pram[0].enet_scc.rbase = 0x0000; */
/*pquicc->pram[0].enet_scc.tbase = 0x0060; */
/* Step 9: Program CPCR to execute the INIT RX TX PARAMS commands */
issue_cmd(INIT_RXTX_PARAMS | (scc_num << 6));
/* Step 10: RFCR and TFCR as normal operation. */
pquicc->pram[0].enet_scc.rfcr = 0x18;
pquicc->pram[0].enet_scc.tfcr = 0x18;
/* Step 11: Max frame length - 0x5f0 (1520) */
/*pquicc->pram[0].enet_scc.mrblr = NET_PARENT_BUFFER_SIZE; */
/*pquicc->pram[0].enet_scc.mrblr = 496; */
pquicc->pram[0].enet_scc.mrblr = (((NET_PARENT_BUFFER_SIZE +4)/4)*4);
/* Step 12: preform 32 bit CCITT-CRC */
pquicc->pram[0].enet_scc.c_pres = 0xffffffff;
/* Step 13: comply with 32 bit CRC */
pquicc->pram[0].enet_scc.c_mask = 0xdebb20e3;
/* Step 14: clear CRCEC, ALEC and DISFC */
pquicc->pram[0].enet_scc.crcec = 0;
pquicc->pram[0].enet_scc.alec = 0;
pquicc->pram[0].enet_scc.disfc = 0;
/* Step 15: padding value */
pquicc->pram[0].enet_scc.pads = 0x8888;
/* Step 16: retry 15 times to send a frame before interrupting */
pquicc->pram[0].enet_scc.ret_lim = 0xf;
/* Stet 17: 1518 max frame size */
pquicc->pram[0].enet_scc.mflr = 1518;
/* Step 18: Minimum frame size 64 */
pquicc->pram[0].enet_scc.minflr = 64;
/* Step 19: Max dma count 1518 */
pquicc->pram[0].enet_scc.maxd1 = 1518;
pquicc->pram[0].enet_scc.maxd2 = 1518;
/* Step 22: P_PER is not used and set to be 0. */
pquicc->pram[0].enet_scc.p_per = 0;
/* Step 20, 21, 23, 24: clear GADDR, IADDR & TADDR, set PADDR */
/*PQUICC_Get_Address(ether_addr, 0); */
PQUICC_Set_Address(device->dev_mac_addr, device);
/*** INITIALIZE SCC REGISTERS AREA ***/
pquicc->scc_regs[0].scc_scce = 0xffff;
/* Step 28: enable TXE, RXF and RXB events. */
pquicc->scc_regs[0].scc_sccm = 0x0019;
/* Step 29: Set the CP mask register to accept interrupts from SCC1. */
pquicc->cpmi_cimr |= INTR_SCC1;
/* Step 30: clear GSMR_H1 to enable normal operation of all modes. */
pquicc->scc_regs[0].scc_gsmra = 0x00000180;
/* Step 31: Write 0x1088000c to GSMR_L1. */
pquicc->scc_regs[0].scc_gsmrb = 0x0088000c;
/* Step 32: DSR, SCC data sync reg */
pquicc->scc_regs[0].scc_dsr = 0xd555;
/* Step 33: protocol specific mode register */
pquicc->scc_regs[0].scc_psmr = 0x080a;
/* Step 34: enable TENA pin, PB19/RST1=E_TENA. */
pquicc->pip_pbdir |= 0x1000;
pquicc->pip_pbpar |= 0x1000;
/* Step 35: Write 0x1088003c to GSMR_L1. */
/* Start I/O operations. enable SCC receive/transmit operation */
pquicc->scc_regs[0].scc_gsmra = 0x1088003c;
/* Step 36: set interrupt level as 4 and enable CPM interrupt. */
pquicc->cpmi_cicr = 0x939f80;
/* Step 37:
after set SCC interrupt level, set its corresponding mask in SIMASK */
simask = (unsigned long *) (immr + 0x14); /* SIU Interrupt Mask */
*simask |= 0x00400000;
/* Clear Interrupts in CIPR -- Clear bits by writing 1. */
pquicc->cpmi_cipr = ~(0x0);
#ifdef ADS /*code for EEST */
/* Step 38:
Setup port C to control EEST: PC4=ETHLOOP, PC5=TPFLDL~, PC6=TPSQEL~ */
pquicc->pio_pcpar &= ~(0x0e00);
pquicc->pio_pcdir |= (0x0e00);
/* LOOP/PC4=0 */
pquicc->pio_pcdat &= ~(0xc00);
/* Deassert: TPFLDL/PC5=TPSQEL/PC6=1 */
pquicc->pio_pcdat |= (0x600);
/* Step 39: Assert CS2 of EEST to enable EEST. */
/* get the address of BR1 */
bcsr1 = (unsigned long *) (immr + 0x108);
/* Get the address of BCSR1 */
bcsr1 = (unsigned long *) ((*bcsr1 & 0xfffffffe) + 4);
/* enable Ethernet EEST (CS2~) by reset EthEn~ bit2 of BCSR1. */
*bcsr1 &= 0xdfffffff;
#endif /* ADS */
#ifdef MBX
pquicc->pio_pcpar |=(1<<0);
pquicc->pio_pcdir &=(1<<0);
pquicc->pio_pcdat &= ~(0xc00);
pquicc->pio_pcdat |= (0x600);
*((uchar *)0xfa100000) |= ((1<<7) | (1<<4) | (1<<3));
#endif /* MBX */
return(0);
} /* PQUICC_Open */
/****************************************************************************/
/* FUNCTION */
/* */
/* PQUICC_Init */
/* */
/* DESCRIPTION */
/* */
/* */
/* AUTHOR */
/* */
/* Bill Haggerty Accelerated Technology Inc. */
/* */
/* CALLED BY */
/* */
/* Application */
/* */
/* CALLS */
/* */
/* PQUICC_Open */
/* */
/* INPUTS */
/* */
/* device pointer : device to use */
/* */
/* OUTPUTS */
/* */
/* None */
/* */
/* HISTORY */
/* */
/* NAME DATE REMARKS */
/* */
/* B. Haggerty 05-07-1998 Created version 1.0 */
/* */
/****************************************************************************/
STATUS PQUICC_Init (DV_DEVICE_ENTRY *device)
{
/* Initialize the various function pointers */
device->dev_open = PQUICC_Open;
device->dev_start = PQUICC_Xmit_Packet;
device->dev_output = NET_Ether_Send;
device->dev_input = NET_Ether_Input;
device->dev_ioctl = PQUICC_Ioctl;
device->dev_type = DVT_ETHER;
device->dev_addrlen = 6;
device->dev_hdrlen = 14; /* Size of an ethernet header. */
device->dev_mtu = 1500; /* MTU excludes the size of the MAC
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