vdevicecfg_c.c

此例程是关于DSP虚拟仪器的程序

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT VDevice.cdb */

/*  Include Header File  */
#include "VDevicecfg.h"


#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")
/*  Config Structures */
MCBSP_Config mcbspCfg0 = {
    0x1000,        /*  Serial Port Control Register 1   */
    0x0061,        /*  Serial Port Control Register 2   */
    0x0040,        /*  Receive Control Register 1   */
    0x0001,        /*  Receive Control Register 2   */
    0x0040,        /*  Transmit Control Register 1   */
    0x0001,        /*  Transmit Control Register 2   */
    0x0013,        /*  Sample Rate Generator Register 1   */
    0x2013,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0a0a,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000         /*  Transmit Channel Enable Register Partition B   */
};

MCBSP_Config mcbspCfg2 = {
    0x0000,        /*  Serial Port Control Register 1   */
    0x0200,        /*  Serial Port Control Register 2   */
    0x00a0,        /*  Receive Control Register 1   */
    0x0044,        /*  Receive Control Register 2   */
    0x00a0,        /*  Transmit Control Register 1   */
    0x0044,        /*  Transmit Control Register 2   */
    0x0077,        /*  Sample Rate Generator Register 1   */
    0x207c,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0003,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000         /*  Transmit Channel Enable Register Partition B   */
};

PLL_Config pllCfg0 = {
    0x2,        /*  PLL Multipler/Divider Mode   */
    0xC8,        /*  PLL Counter Value (PLLCOUNT)   */
    0x5,        /*  PLL Multiplier Value (PLLMUL)   */
    0x1         /*  CLKOUT Output Divide Factor (DIVFCT)   */
};

TIMER_Config timerCfg0 = {
    0x0000,        /*  Timer Control Register   */
    0x0000         /*  Timer Period Register   */
};

/*  Handles  */
MCBSP_Handle hMcbsp0;
MCBSP_Handle hMcbsp2;

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
    hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
    hMcbsp2 = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
    MCBSP_config(hMcbsp0, &mcbspCfg0);
    MCBSP_config(hMcbsp2, &mcbspCfg2);
    PLL_config(&pllCfg0);




}