📄 9s08gb_gt_irgtrim_9600.asm
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;*********************************************************************
;* Filename: 9S08GB_GT_IRGTRIM_9600.asm Copyright (c) Motorola 2003
;*********************************************************************
;*********************************************************************
;* Oscillator Trim Routine for 9S08GB/GT Family Bill Lucas/Scott Pape
;*
;* Rev: 1.0 Date: 18July2002 Scott Pape
;* Rev: 1.1 Date: 2January2003 Bill Lucas Ported from QTx to 9S08GB/GT
;*
;* This program, will trim the internal 243 kHz ICG reference
;* oscillator. The ICG is set to run from the 243 kHz internal
;* oscillator with the FLL engaged to clock the CPU bus at 1.6663 MHz.
;* Timer 1 channel 0 is used to measure the period of an external 9600
;* baud calibration reference clock. Timer 1 channel 1 is used to
;* output 10% of the 1.6663 MHz CPU bus frequency after the
;* calibration process.
;*
;* The ICGTRM value is modified if the measured value is higher or
;* lower than the expected value. Once the proper trim value is found,
;* it is programmed into the NVICGTRIM (located at $FFBE) storage
;* location in Flash. The user code MUST copy the value of NVICGTRIM
;* into the ICG ICGTRM register at the beginning of his application
;* code.
;*
;* Usage Notes:
;* 1. This program requires a 9600 baud reference signal connected to
;* Timer 1, channel 0 (PTD0/TPM1CH0), or the timer of your choice.
;* 2. The program assumes Flash at location NVICGTRIM ($FFBE) is
;* erased.
;* 3. Code for this program is loaded into and executes in RAM.
;* 4. After loading the code into RAM and connecting the 9600 baud
;* signal to timer 1 channel 0, through the debugger, execute a
;* RESET and GO 80 command.
;* 5. At the conclusion of successful ICG calibration, 10% of the bus
;* clock frequency will be outputto timer 1 channel 1 The frequency
;* of timer 1 channel 1 will be very close to 166.63 kHz. If an
;* error occurs because Flash at NVICGTRIM was not errased or a
;* Flash programming error was detected timer 1 channel 1,will
;* toggle in the range from 12.4 kHz to 20.8 kHz, indicating the
;* error.
;*********************************************************************
;*********************************************************************
;*
;* Motorola reserves the right to make changes without further notice
;* to any product herein to improve reliability, function, or design.
;* Motorola does not assume any liability arising out of the
;* application or use of any product, circuit, or software described
;* herein; neither does it convey any license under its patent rights
;* nor the rights of others. Motorola products are not designed,
;* intended, or authorized for use as components in systems intended
;* for surgical implant into the body, or other applications intended
;* to support life, or for any other application in which the failure
;* of the Motorola product could create a situation where personal
;* injury or death may occur. Should Buyer purchase or use Motorola
;* products for any such intended or unauthorized application, Buyer
;* shall indemnify and hold Motorola and its officers, employees,
;* subsidiaries, affiliates, and distributors harmless against all
;* claims, costs, damages, and expenses, and reasonable attorney fees
;* arising out of, directly or indirectly, any claim of personal
;* injury or death associated with such unintended or unauthorized
;* use, even if such claim alleges that Motorola was negligent
;* regarding the design or manufacture of the part.
;*
;* Motorola and the Motorola logo are registered trademarks of
;* Motorola, Inc.
;*********************************************************************
;
;*** include 9S08GB60 equate file ************************************
include "9S08GB60v1r3.inc" ;I/O definitions
;
;*** Begining of RAM Memory ******************************************
org RamStart
bra Start
;
;*** equates for RAM variables and Constants *************************
SyncOffsetH: ds 1 ;Timer offset hi byte
SyncOffsetL: ds 1 ;Timer offset lo byte
ActualH: ds 1 ;Timer count hi byte
ActualL: ds 1 ;Timer count lo byte
Delta: ds 1 ;Actual delta from expected
LoopCnt: ds 1 ;Count how many measurements taken
Adjust: equ $0 ;Adjust offset to get val $100-$1FF
ExpectedH: equ $1 ;range is $104->1B2, ideal = $15B
ExpectedL: equ $5B-Adjust ;Expected Timer value if trimmed
stack: equ $87F ;This will work for GB/GT 32 or 60
byte_pgm: equ $20 ;Command to program a single byte
zero: equ 0 ;Constant 0
one: equ 1 ;Constant 1
four: equ 4 ;Constant 4
forty_nine equ 49 ;Constant 49
;******* include "9S08GB_GT_Timer_Selection.h" ;IC/OC timer *******
nolist
include "9S08GB_GT_Timer_Selection.inc" ;IC/OC timer
list
;*** Main ************************************************************
Start: ldhx #stack
txs ;SP<-(H:X)
lda SOPT
and #(mCOPT|mBKGDPE)
sta SOPT ;disable the COP
mov #mCLKSA,OUT_TPMxSC ;Use BUSCLK as timer clock
mov #(mREFS|mCLKS0),ICGC1 ;xtal and FLL internal
mov #(mMFD0|mRFD1),ICGC2 ;multiply by 6 and div by 4
lock_loop: brclr LOCK,ICGS1,lock_loop ;wait for FLL lock @ 1.6 MHz
lda NVICGTRIM ;Current stored Trim value.
coma ;$FF -> $00
bne Trim_error ;If Trim <> $FF, Not erased skip cal
clr LoopCnt ;Initialize the iteration counter
TryAgain: clr ActualH
clr ActualL
clr Delta
inc LoopCnt ;Increment iteration count
mov #(mCLKSA),IN_TPMxSC ;bus clk & div by 1
mov #mELS1A,IN_TPMxCnSC ;capture on rising edge only
lda IN_TPMxCnSC ;dummy read of the status register
bclr CH0F,IN_TPMxCnSC ;complete clearing if it was set
loop:
jsr read_timer ;get the first edge
sthx SyncOffsetH ;save for later
jsr read_timer ;get the second edge
txa ;low byte of secont edge time
sub SyncOffsetL ;compute the time difference
sta ActualL ;low byte of Actual
pshh ;high byte of second edge time
pula
sbc SyncOffsetH
sta ActualH ;high byte of Actual
lda ActualL ;Adjust the Actual value so...
sub #Adjust ;...the range fits into 1 byte
sta ActualL
cmp #ExpectedL ;Compare Actual with Expected value
beq GotTrim ;If equal, osc is trimmed!
blo TooSlow ;If lower, osc is too slow
sub #ExpectedL ;Otherwise, osc is too fast
sta Delta ;Calculate Delta from Act-Exp
lda ICGTRM
cmp #$FF ;Check if trim=$FF
beq GotTrim ;if true, can't slow more
brset 5,LoopCnt,GotTrim ;bit5=32 loops=limit
brclr 4,LoopCnt,AddDelta ;bit4 = 16 loops
mov #$01,Delta ;after 8 loops, just add 1
AddDelta: add Delta ;acca still has OSCTRIM
bcc AddTrim ;did carry bit get set?
lda #$FF ;if carry set, max osctrim
AddTrim: sta ICGTRM ;Trim increases to slow freq
bra TryAgain ;Try new value
TooSlow: lda #ExpectedL
sub ActualL
sta Delta ;Calculate Delta from Exp-Act
lda ICGTRM
beq GotTrim ;if true, can't speed-up more
brset 5,LoopCnt,GotTrim ;bit5=32 loops=limit
brclr 4,LoopCnt,SubDelta ;bit4 = 16 loops
mov #$01,Delta ;after 8 loops, just add 1
SubDelta: sub Delta
bcc SubTrim ;did carry bit get set?
lda #$FF ;if carry set, min osctrim
SubTrim: sta ICGTRM
bra TryAgain
;******* Toggle PTD1 @ 12.4 kHz to 20.8 kHz if we have an error ******
;* There are two reasons to be here:
;* 1). NVICGTRIM is not errased
;* 2). There was a Flash error during prog'ing. This error is rare.
; The following timer code will output 1% of the CPU BUSCLOCK to
; the selected output compare channel for ICG frequency monitoting
Trim_error: lda NVICGTRIM ;Current Trim value.
sta ICGTRM ;Use the value that's there
mov #mCLKSA,OUT_TPMxSC ;Use BUSCLK as timer clock
mov #(mMS1A|mELS1A),OUT_TPMxCnSC ;Toggle on output cmp
mov #zero,OUT_TPMxMODH
mov #forty_nine,OUT_TPMxMODL ;Timer modulo reg = 49
mov #zero,OUT_TPMxCnVH
mov #one,OUT_TPMxCnVL ;Timer output compare at 1
bra $ ;Let the output TPM pin toggle
;at 1% of BUSCLOCK to indicate error
;*** Program Trim Value to Flash *************************************
GotTrim: bsr PrgTrim ;Program the Trim value
lda NVICGTRIM ;Read value from Flash to make sure
sta ICGTRM ;Verf trim value is prog'ed in flash
; The following timer code will output 10% of the CPU BUSCLOCK to
; the selected output compare channel for ICG frequency monitoting
mov #(mMS1A|mELS1A),OUT_TPMxCnSC ;Toggle on output cmp
mov #zero,OUT_TPMxMODH
mov #four,OUT_TPMxMODL ;Timer modulo register = 4
mov #zero,OUT_TPMxCnVH
mov #one,OUT_TPMxCnVL ;Timer output compare at 1
bra $ ;Let selected output TPM pin toggle
; at 10% of BUSCLOCK to indicate completion
;*** Subroutines ProgTrim ********************************************
;* Changed for GB/GT Flash WLL
; PrgTrim:
; Programs the value in the ICGTRM register into the reserved Flash
; location for the trim value, NVICGTRIM @ $FFBE.
; Entry Conditions:
; 1. The NVICGTRIM ($FFBE) location in flash is erased ($FF).
; 2. The ICGTRM register contains the desired trim value.
;
; Exit conditions:
; 1. NVICGTRIM is programmed with the value in ICGTRM.
; 2. ICGTRM is not modified.
; 3. no registers altered
;
PrgTrim: psha
lda #mFPVIOL|mFACCERR ;error flag bits to clear if set
sta FSTAT ;clear any error flags
lda #mDIV3 ;1.666 MHz/8+1 = 185Khz Flash clock
sta FCDIV ;divide by 8+1 for 1.66 MHz bus.
; This is normally done at start-up, however we
; will initialize here to only program one byte
lda ICGTRM ;trim value
sta NVICGTRIM ;place in Flash
lda #byte_pgm ;page write command
sta FCMD ;initiate the programming sequence
lda FSTAT
ora #mFCBEF
sta FSTAT ;launch the command
brn * ;burn bus cycs before chking status
lda FSTAT ;look at status register for errors
and #mFPVIOL|mFACCERR ;error flag bits
bne Trim_error ;check for programming errors
pgm_loop: lda FSTAT ;wait around unil prog'ing complete
and #mFCCF ;command complete yet?
beq pgm_loop ;not done yet..loop until complete
pula
EndPrgTrim: rts ;done
;*** Subroutine read_timer *******************************************
;* Changed for TB/GT device WLL
; read_timer:
; Waits for a reference clock positive giong edge, reads the captured
; value into H:X, clears the input capture flag and returns the timer
; capture value in register H:X.
; Entry Conditions:
; None
;
; Exit conditions:
; Register A destroyed, register X contains the captured timer value
;
read_timer: brclr CH0F,IN_TPMxCnSC,read_timer ;loop until see edge
ldhx IN_TPMxCnVH ;get the counter value
lda IN_TPMxCnSC ;dummy read of the status register
bclr CH0F,IN_TPMxCnSC ;complete the clearing process
rts
END
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