📄 vid_hist.mdl
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Line {
SrcBlock "Matrix\nConcatenation1"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "RGB Video"
SrcPort 1
DstBlock "Display"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "RGB Video"
DstPort 1
}
Line {
SrcBlock "R"
SrcPort 1
DstBlock "Matrix\nConcatenation1"
DstPort 1
}
Line {
SrcBlock "G"
SrcPort 1
DstBlock "Matrix\nConcatenation1"
DstPort 2
}
Line {
SrcBlock "B"
SrcPort 1
DstBlock "Matrix\nConcatenation1"
DstPort 3
}
}
}
Block {
BlockType Reference
Name "Signal From\nWorkspace"
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Position [15, 16, 65, 44]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "vR3"
Ts "1/30"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace1"
Ports [0, 1]
Position [15, 46, 65, 74]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "vG3"
Ts "1/30"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace2"
Ports [0, 1]
Position [15, 76, 65, 104]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "vB3"
Ts "1/30"
nsamps "1"
OutputAfterFinalValue "Cyclic repetition"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType SubSystem
Name "Single Column"
Ports [1, 1]
Position [215, 244, 265, 286]
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Single Column"
Location [552, 218, 896, 316]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In"
Position [25, 25, 55, 45]
NamePlacement "alternate"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [175, 21, 230, 49]
ShowName off
OutDataTypeMode "single"
OutDataTypeStr "single"
}
Block {
BlockType Reshape
Name "Reshape"
Position [100, 23, 130, 47]
ShowName off
}
Block {
BlockType Outport
Name "Out"
Position [270, 28, 300, 42]
IconDisplay "Port number"
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Out"
DstPort 1
}
Line {
SrcBlock "In"
SrcPort 1
DstBlock "Reshape"
DstPort 1
}
Line {
SrcBlock "Reshape"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "To Single"
Ports [1, 1]
Position [215, 189, 265, 231]
ShowName off
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "To Single"
Location [552, 218, 896, 316]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In"
Position [25, 25, 55, 45]
NamePlacement "alternate"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [175, 21, 230, 49]
ShowName off
OutDataTypeMode "single"
OutDataTypeStr "single"
}
Block {
BlockType Reshape
Name "Reshape"
Position [100, 23, 130, 47]
ShowName off
}
Block {
BlockType Outport
Name "Out"
Position [270, 28, 300, 42]
IconDisplay "Port number"
}
Line {
SrcBlock "Reshape"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "In"
SrcPort 1
DstBlock "Reshape"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Out"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "To Single1"
Ports [1, 1]
Position [215, 134, 265, 176]
ShowName off
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "To Single1"
Location [552, 218, 896, 316]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In"
Position [25, 25, 55, 45]
NamePlacement "alternate"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [175, 21, 230, 49]
ShowName off
OutDataTypeMode "single"
OutDataTypeStr "single"
}
Block {
BlockType Reshape
Name "Reshape"
Position [100, 23, 130, 47]
ShowName off
}
Block {
BlockType Outport
Name "Out"
Position [270, 28, 300, 42]
IconDisplay "Port number"
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Out"
DstPort 1
}
Line {
SrcBlock "In"
SrcPort 1
DstBlock "Reshape"
DstPort 1
}
Line {
SrcBlock "Reshape"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
}
}
Line {
SrcBlock "Signal From\nWorkspace"
SrcPort 1
Points [0, 0; 115, 0]
Branch {
Points [0, 125]
DstBlock "To Single1"
DstPort 1
}
Branch {
DstBlock "Show RGB"
DstPort 1
}
}
Line {
SrcBlock "Signal From\nWorkspace1"
SrcPort 1
Points [0, 0; 95, 0]
Branch {
Points [0, 150]
DstBlock "To Single"
DstPort 1
}
Branch {
DstBlock "Show RGB"
DstPort 2
}
}
Line {
SrcBlock "Signal From\nWorkspace2"
SrcPort 1
Points [0, 0; 75, 0]
Branch {
Points [0, 175]
DstBlock "Single Column"
DstPort 1
}
Branch {
DstBlock "Show RGB"
DstPort 3
}
}
Line {
SrcBlock "To Single"
SrcPort 1
DstBlock "Histo Green"
DstPort 1
}
Line {
SrcBlock "To Single1"
SrcPort 1
DstBlock "Histo Red"
DstPort 1
}
Line {
SrcBlock "Single Column"
SrcPort 1
DstBlock "Histo Blue"
DstPort 1
}
Line {
Name "Red"
Labels [-1, 0]
SrcBlock "Histo Red"
SrcPort 1
Points [10, 0; 0, 40]
DstBlock "Matrix\nConcatenation"
DstPort 1
}
Line {
Name "Green"
Labels [-1, 0]
SrcBlock "Histo Green"
SrcPort 1
DstBlock "Matrix\nConcatenation"
DstPort 2
}
Line {
Name "Blue"
Labels [-1, 0]
SrcBlock "Histo Blue"
SrcPort 1
Points [10, 0; 0, -40]
DstBlock "Matrix\nConcatenation"
DstPort 3
}
Line {
SrcBlock "Matrix\nConcatenation"
SrcPort 1
DstBlock "RGB\nHistogram"
DstPort 1
}
}
}
MatData {
NumRecords 6
DataRecord {
Tag DataTag5
Data " %)30 . , 8 ( ! % \" 0 0 "
}
DataRecord {
Tag DataTag4
Data " %)30 . < 8 ( 0 % \" $ ! 0 . 0 8 ( ! "
" % \" $ ) 0 0 \"0 $AI<W1O9W)A;0 "
}
DataRecord {
Tag DataTag3
Data " %)30 . < 8 ( 0 % \" $ ! 0 . 0 8 ( ! "
" % \" $ ) 0 0 \"0 $AI<W1O9W)A;0 "
}
DataRecord {
Tag DataTag2
Data " %)30 . < 8 ( 0 % \" $ ! 0 . 0 8 ( ! "
" % \" $ ) 0 0 \"0 $AI<W1O9W)A;0 "
}
DataRecord {
Tag DataTag1
Data " %)30 . < 8 ( 0 % \" $ ! 0 . 0 8 ( ! "
" % \" $ / 0 0 #P &9R;VUV:61E;V1E=FEC90 "
}
DataRecord {
Tag DataTag0
Data " %)30 . * 0 8 ( @ % \" $ ! 0 % 0 %@ $ ( 0 0F%C:V"
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"<&]S=7)E !&<F%M95)A=&4 1V%M;6$ $AU90 "
"!3871U<F%T:6]N 4VAA<G!N97-S %1A9P !7:&ET94)A;&%N8V4 "
" #@ # & \" 0 !0 @ ! @ $ $ \" &]N . . 8 ( !@ %"
" \" $ ! 0 ) \" #1 #@ # & \" 0 !0 @ ! @ $ "
" $ \" &]N . . 8 ( !@ % \" $ ! 0 ) \" #1 #@ #@ "
" & \" 8 !0 @ ! 0 $ \"0 @ #P/PX X !@ @ $ 4 "
" ( 0 < ! ! ' ,S N,# P, . . 8 ( !@ % \" $ ! 0 "
") \" !! #@ #@ & \" 8 !0 @ ! 0 $ \"0 @ R0 X "
" X !@ @ & 4 ( 0 $ ! D ( 24 . . 8 ( !@ %"
" \" $ ! 0 ) \" A #@ # & \" 0 !0 @ $ "
" $ . . 8 ( !@ % \" $ ! 0 ) \" / _"
}
}
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