renbjq.vhd

来自「实现7人表决功能」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity renbjq is
port(d:in std_logic_vector(6 downto 0);
     f:out std_logic);
end renbjq;
architecture behav of renbjq is
    signal i1,i2:std_logic_vector(2 downto 0);
begin
    i1<="00"&d(0);
    i2<=i1+d(1)+d(2)+d(3)+d(4)+d(5)+d(6);
f<='0' when(i2<4)
else '1';
end behav;