startup.s

致远的MagicARM2410上的关于ARM的所有实验代码

;/****************************************Copyright (c)**************************************************
;**                               Guangzhou ZHIYUAN electronics Co.,LTD.
;**                                     
;**                                 http://www.zyinside.com
;**
;**--------------File Info-------------------------------------------------------------------------------
;** File Name: startup.s
;** Last modified Date: 2005-10-21
;** Last Version: v0.1
;** Description: S3C2410异常向量入口及异常向量与c语言代码的接口，包括初始化堆栈的代码
;**
;**------------------------------------------------------------------------------------------------------
;** Created By: 黄绍斌
;** Created date: 2005-10-21
;** Version: v0.1
;** Descriptions:
;**
;**------------------------------------------------------------------------------------------------------
;** Modified by:
;** Modified date:
;** Version:
;** Description:
;**
;********************************************************************************************************/

; /* 定义堆栈的大小 */
; **** 用户可根据实际需要修改 ****
USR_STACK_LEGTH     EQU         64
SVC_STACK_LEGTH     EQU         0
FIQ_STACK_LEGTH     EQU         16
IRQ_STACK_LEGTH     EQU         16
ABT_STACK_LEGTH     EQU         0
UND_STACK_LEGTH     EQU         0

; 总线宽度控制定义(0表示8位，1表示16位，2表示32位)
DW8					EQU			(0x0)
DW16				EQU			(0x1)
DW32				EQU			(0x2)
WAIT				EQU			(0x1<<2)
UBLB				EQU			(0x1<<3)

B7_BWCON			EQU			(DW16|WAIT|UBLB) 
B6_BWCON			EQU			(DW32|UBLB)  
B5_BWCON			EQU			(DW16|WAIT|UBLB)  
B4_BWCON			EQU			(DW16|WAIT|UBLB)  
B3_BWCON			EQU			(DW16|WAIT|UBLB)  
B2_BWCON			EQU			(DW16|WAIT|UBLB)  
B1_BWCON			EQU			(DW16|WAIT|UBLB)  

; CPU时钟设置(PLLCON控制值)
; 50.00 MHz 
MDIV_50				EQU		0x5C
PDIV_50				EQU		0x4
SDIV_50				EQU		0x2

; 200.00 MHz (m=100,p=6,s=0, MPLL=FCLK=12*100/6=200MHz)
MDIV_200			EQU		0x5C
PDIV_200			EQU		0x4
SDIV_200			EQU		0x0
		
MPLLCON_200			EQU		((MDIV_200 << 12) | (PDIV_200 << 4) | (SDIV_200)) 


; 引入的外部标号在这声明
	IMPORT  __main                          ;C语言主程序入口 
	

; 给外部使用的标号在这声明
    EXPORT  Vectors    
    EXPORT  Reset
    EXPORT __rt_div0
    EXPORT __user_initial_stackheap
    
    
;/*************************************************************************/
;/* CPSR寄存器的位域                                                      */
;/*************************************************************************/
;/*                                                                       */
;/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*                                                                       */
;/* Processor Mode and Mask                                               */
;/*                                                                       */
;/*************************************************************************/
Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F 

I_BIT           EQU     0x80 	; when I bit is set (1), IRQ is disabled
F_BIT           EQU     0x40 	; when F bit is set (1), FIQ is disabled


; 寄存器定义
;=================
; WATCH DOG TIMER
;=================
WTCON     		EQU  	0x53000000     	;Watch-dog timer mode
WTDAT     		EQU  	0x53000004      ;Watch-dog timer data
WTCNT    	 	EQU  	0x53000008      ;Eatch-dog timer count

;=================
; INTERRUPT
;=================
SRCPND       	EQU  	0x4a000000    	;Interrupt request status
INTMOD       	EQU  	0x4a000004    	;Interrupt mode control
INTMSK       	EQU  	0x4a000008    	;Interrupt mask control
PRIORITY     	EQU  	0x4a00000c    	;IRQ priority control  
INTPND       	EQU  	0x4a000010    	;Interrupt request status
INTOFFSET    	EQU  	0x4a000014    	;Interruot request source offset
SUSSRCPND    	EQU  	0x4a000018    	;Sub source pending
INTSUBMSK    	EQU  	0x4a00001c    	;Interrupt sub mask

;=================
; Memory control 
;=================
BWSCON      	EQU  	0x48000000     ;Bus width & wait status
BANKCON0    	EQU  	0x48000004     ;Boot ROM control
BANKCON1    	EQU  	0x48000008     ;BANK1 control
BANKCON2    	EQU  	0x4800000c     ;BANK2 cControl
BANKCON3    	EQU  	0x48000010     ;BANK3 control
BANKCON4    	EQU  	0x48000014     ;BANK4 control
BANKCON5    	EQU  	0x48000018     ;BANK5 control
BANKCON6    	EQU  	0x4800001c     ;BANK6 control
BANKCON7    	EQU  	0x48000020     ;BANK7 control
REFRESH     	EQU  	0x48000024     ;DRAM/SDRAM refresh
BANKSIZE    	EQU  	0x48000028     ;Flexible Bank Size
MRSRB6      	EQU  	0x4800002c     ;Mode register set for SDRAM
MRSRB7      	EQU  	0x48000030     ;Mode register set for SDRAM

;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME    	EQU  	0x4c000000     ;PLL lock time counter
MPLLCON     	EQU  	0x4c000004     ;MPLL Control
UPLLCON     	EQU  	0x4c000008     ;UPLL Control
CLKCON      	EQU  	0x4c00000c     ;Clock generator control
CLKSLOW     	EQU  	0x4c000010     ;Slow clock control
CLKDIVN     	EQU  	0x4c000014     ;Clock divider control





; /************************************************************************/
    	CODE32
   		AREA    Startup,CODE,READONLY
; 异常向量表
Vectors
        LDR     PC, ResetAddr
        LDR     PC, UndefinedAddr
        LDR     PC, SWI_Addr
        LDR     PC, PrefetchAddr
        LDR     PC, DataAbortAddr
        DCD     IRQ_Addr
        LDR     PC, [PC, #-0xff0]
        LDR     PC, FIQ_Addr

ResetAddr           DCD     Reset
UndefinedAddr       DCD     Undefined
SWI_Addr            DCD     SoftwareInterrupt
PrefetchAddr        DCD     PrefetchAbort
DataAbortAddr       DCD     DataAbort
Nouse               DCD     0
IRQ_Addr            DCD     IRQ_Handler
FIQ_Addr            DCD     FIQ_Handler

;未定义指令
Undefined
        B       Undefined

;软中断
SoftwareInterrupt
        B       SoftwareInterrupt

PrefetchAbort
        B       PrefetchAbort

;取数据中止
DataAbort
        B       DataAbort
        
;IRQ中断
IRQ_Handler
		STMFD   SP!, {R0-R3, LR}
        
        ; /* FIQ中断处理 */
        
        LDMFD   SP!, {R0-R3, LR}       		
		SUBS	PC, LR, #4


;快速中断
FIQ_Handler
        STMFD   SP!, {R0-R3, LR}
        
        ; /* FIQ中断处理 */
        
        LDMFD   SP!, {R0-R3, LR}