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>Motorola PrPMC1100 CPU card</TITLE
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><DIV
CLASS="SECT1"
><H1
CLASS="SECT1"
><A
NAME="PRPMC1100"
>Motorola PrPMC1100 CPU card</A
></H1
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5056"
>Overview</A
></H2
><P
>RedBoot supports
the builtin high-speed and console UARTs
.
The console UART is the default and feeds the front panel COM1 connector. The
high-speed UART signals are only available from the PN4 IO connector. Therefore,
usability of this port depends on the carrier board used. The default serial
port settings are 115200,8,N,1. RedBoot also supports flash management for
the 16MB boot flash on the mainboard.</P
><P
>The following RedBoot configurations are supported:
<DIV
CLASS="INFORMALTABLE"
><P
></P
><A
NAME="AEN5066"
></A
><TABLE
BORDER="1"
FRAME="border"
RULES="all"
CLASS="CALSTABLE"
><COL><COL><COL><COL><THEAD
><TR
><TH
>Configuration</TH
><TH
>Mode</TH
><TH
>Description</TH
><TH
>File</TH
></TR
></THEAD
><TBODY
><TR
><TD
>ROM</TD
><TD
>[ROM]</TD
><TD
>RedBoot running from flash
sector.</TD
><TD
>redboot_ROM.ecm</TD
></TR
><TR
><TD
>RAM</TD
><TD
>[RAM]</TD
><TD
>RedBoot running from RAM with RedBoot in the
flash boot sector.</TD
><TD
>redboot_RAM.ecm</TD
></TR
></TBODY
></TABLE
><P
></P
></DIV
></P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5085"
>Initial Installation Method</A
></H2
><P
>The PrPMC1100 flash is socketed, so initial installation may be done using
an appropriate device programmer. JTAG based flash programming may also be used.
In either case, the ROM mode RedBoot is programmed into the boot flash at address
0x00000000.</P
><P
>After booting the initial installation of RedBoot, this warning may
be printed: <TABLE
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><TR
><TD
><PRE
CLASS="SCREEN"
>flash configuration checksum error or invalid key</PRE
></TD
></TR
></TABLE
>This is normal, and indicates that the flash should be configured
for use by RedBoot. Even if this message is not seen, it is recommended that
the <B
CLASS="COMMAND"
>fconfig</B
> be run to initialize the flash configuration
area. See <A
HREF="persistent-state-flash.html"
>the Section called <I
>Persistent State Flash-based Configuration and Control</I
> in Chapter 2</A
> for more details.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5092"
>Rebuilding RedBoot</A
></H2
><P
>These shell variables provide the platform-specific information
needed for building RedBoot according to the procedure described in
<A
HREF="rebuilding-redboot.html"
>Chapter 3</A
>:
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>export TARGET=prpmc1100
export ARCH_DIR=arm
export PLATFORM_DIR=xscale/prpmc1100</PRE
></TD
></TR
></TABLE
></P
><P
>The names of configuration files are listed above with the
description of the associated modes.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5098"
>Interrupts</A
></H2
><P
>RedBoot uses an interrupt vector table which is located at address 0x8004.
Entries in this table are pointers to functions with this protoype:: <TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>int irq_handler( unsigned vector, unsigned data )</PRE
></TD
></TR
></TABLE
>On the PrPMC1100
board, the vector argument is one of many interrupts defined in <SAMP
CLASS="COMPUTEROUTPUT"
>hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</SAMP
>: <TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>#define CYGNUM_HAL_INTERRUPT_NPEA 0
#define CYGNUM_HAL_INTERRUPT_NPEB 1
#define CYGNUM_HAL_INTERRUPT_NPEC 2
#define CYGNUM_HAL_INTERRUPT_QM1 3
#define CYGNUM_HAL_INTERRUPT_QM2 4
#define CYGNUM_HAL_INTERRUPT_TIMER0 5
#define CYGNUM_HAL_INTERRUPT_GPIO0 6
#define CYGNUM_HAL_INTERRUPT_GPIO1 7
#define CYGNUM_HAL_INTERRUPT_PCI_INT 8
#define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9
#define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10
#define CYGNUM_HAL_INTERRUPT_TIMER1 11
#define CYGNUM_HAL_INTERRUPT_USB 12
#define CYGNUM_HAL_INTERRUPT_UART2 13
#define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14
#define CYGNUM_HAL_INTERRUPT_UART1 15
#define CYGNUM_HAL_INTERRUPT_WDOG 16
#define CYGNUM_HAL_INTERRUPT_AHB_PMU 17
#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18
#define CYGNUM_HAL_INTERRUPT_GPIO2 19
#define CYGNUM_HAL_INTERRUPT_GPIO3 20
#define CYGNUM_HAL_INTERRUPT_GPIO4 21
#define CYGNUM_HAL_INTERRUPT_GPIO5 22
#define CYGNUM_HAL_INTERRUPT_GPIO6 23
#define CYGNUM_HAL_INTERRUPT_GPIO7 24
#define CYGNUM_HAL_INTERRUPT_GPIO8 25
#define CYGNUM_HAL_INTERRUPT_GPIO9 26
#define CYGNUM_HAL_INTERRUPT_GPIO10 27
#define CYGNUM_HAL_INTERRUPT_GPIO11 28
#define CYGNUM_HAL_INTERRUPT_GPIO12 29
#define CYGNUM_HAL_INTERRUPT_SW_INT1 30
#define CYGNUM_HAL_INTERRUPT_SW_INT2 31</PRE
></TD
></TR
></TABLE
>
The data passed to the ISR is pulled from a data table <SAMP
CLASS="COMPUTEROUTPUT"
>(hal_interrupt_data)</SAMP
> which immediately follows the interrupt vector table. With
32 interrupts, the data table starts at address 0x8084. </P
><P
>An application may create a normal C function with the above prototype
to be an ISR. Just poke its address into the table at the correct index and
enable the interrupt at its source. The return value of the ISR is ignored
by RedBoot.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5106"
>Memory Maps</A
></H2
><P
>The RAM based page table is located at RAM start + 0x4000.
<DIV
CLASS="NOTE"
><BLOCKQUOTE
CLASS="NOTE"
><P
><B
>NOTE: </B
>The virtual memory maps in this section use a C, B, and X column to indicate
the caching policy for the region..</P
></BLOCKQUOTE
></DIV
></P
><P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>X C B Description
- - - ---------------------------------------------
0 0 0 Uncached/Unbuffered
0 0 1 Uncached/Buffered
0 1 0 Cached/Buffered Write Through, Read Allocate
0 1 1 Cached/Buffered Write Back, Read Allocate
1 0 0 Invalid -- not used
1 0 1 Uncached/Buffered No write buffer coalescing
1 1 0 Mini DCache - Policy set by Aux Ctl Register
1 1 1 Cached/Buffered Write Back, Read/Write Allocate
Virtual Address Physical Address XCB Size (MB) Description
--------------- ---------------- --- --------- -----------
0x00000000 0x00000000 010 256 SDRAM (cached)
0x10000000 0x10000000 010 256 SDRAM (alias)
0x20000000 0x00000000 000 256 SDRAM (uncached)
0x48000000 0x48000000 000 64 PCI Data
0x50000000 0x50000000 010 16 Flash (CS0)
0x51000000 0x51000000 000 112 CS1 - CS7
0x60000000 0x60000000 000 64 Queue Manager
0xC0000000 0xC0000000 000 1 PCI Controller
0xC4000000 0xC4000000 000 1 Exp. Bus Config
0xC8000000 0xC8000000 000 1 Misc CPU IO
0xCC000000 0xCC000000 000 1 SDRAM Config </PRE
></TD
></TR
></TABLE
></P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5114"
>Platform Resource Usage</A
></H2
><P
>The CPU programmable OStimer0 is used for timeout support
for networking and XModem file transfers.</P
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