📄 rt-arm-ep7211.html
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Timing complete - 30450 ms total
PASS:<Basic timing OK>
EXIT:<done>
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>CPU : Cirrus Logic EP7212 73MHz</A
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>Board: Cirrus Logic EDB7111-2 Development Board
CPU : Cirrus Logic EP7212 73MHz
Startup, main stack : stack used 404 size 2400
Startup : Interrupt stack used 136 size 4096
Startup : Idlethread stack used 88 size 2048
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 356.32 microseconds (182 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 64
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Alarms: 32
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
22.43 15.63 33.20 3.02 68% 18% Create thread
4.48 3.91 5.86 0.81 70% 70% Yield thread [all suspended]
4.42 3.91 7.81 0.78 75% 75% Suspend [suspended] thread
4.12 1.95 5.86 0.49 82% 3% Resume thread
5.62 3.91 11.72 0.64 78% 18% Set priority
2.17 1.95 3.91 0.38 89% 89% Get priority
11.54 9.77 27.34 0.88 70% 25% Kill [suspended] thread
4.64 3.91 9.77 0.96 65% 65% Yield [no other] thread
7.51 5.86 15.63 0.72 76% 21% Resume [suspended low prio] thread
3.88 1.95 9.77 0.42 82% 10% Resume [runnable low prio] thread
7.14 5.86 13.67 1.00 59% 39% Suspend [runnable] thread
4.52 3.91 7.81 0.86 70% 70% Yield [only low prio] thread
4.15 1.95 7.81 0.49 85% 1% Suspend [runnable->not runnable]
11.26 9.77 27.34 1.17 56% 39% Kill [runnable] thread
6.22 3.91 13.67 0.88 70% 7% Destroy [dead] thread
13.64 11.72 33.20 1.02 64% 26% Destroy [runnable] thread
24.17 21.48 41.02 1.49 82% 12% Resume [high priority] thread
8.80 7.81 21.48 1.08 98% 54% Thread switch
1.60 0.00 1.95 0.58 82% 17% Scheduler lock
2.61 1.95 3.91 0.87 66% 66% Scheduler unlock [0 threads]
2.59 1.95 3.91 0.86 67% 67% Scheduler unlock [1 suspended]
2.61 1.95 3.91 0.87 66% 66% Scheduler unlock [many suspended]
2.59 1.95 3.91 0.86 67% 67% Scheduler unlock [many low prio]
2.62 1.95 3.91 0.88 65% 65% Init mutex
4.82 3.91 9.77 1.09 96% 59% Lock [unlocked] mutex
4.39 3.91 9.77 0.79 81% 81% Unlock [locked] mutex
3.84 1.95 7.81 0.36 87% 9% Trylock [unlocked] mutex
3.54 1.95 5.86 0.69 75% 21% Trylock [locked] mutex
1.83 0.00 3.91 0.34 87% 9% Destroy mutex
34.61 31.25 46.88 1.68 78% 9% Unlock/Lock mutex
3.97 1.95 7.81 0.24 93% 3% Create mbox
1.83 0.00 3.91 0.34 87% 9% Peek [empty] mbox
4.76 3.91 9.77 1.07 62% 62% Put [first] mbox
1.71 0.00 3.91 0.64 75% 18% Peek [1 msg] mbox
5.00 3.91 9.77 1.10 96% 50% Put [second] mbox
1.65 0.00 1.95 0.52 84% 15% Peek [2 msgs] mbox
5.31 3.91 11.72 1.05 59% 37% Get [first] mbox
5.13 3.91 7.81 0.99 56% 40% Get [second] mbox
4.76 3.91 11.72 1.12 96% 65% Tryput [first] mbox
4.46 3.91 7.81 0.82 75% 75% Peek item [non-empty] mbox
5.55 3.91 9.77 0.82 68% 25% Tryget [non-empty] mbox
4.03 1.95 7.81 0.58 78% 9% Peek item [empty] mbox
4.27 3.91 5.86 0.59 81% 81% Tryget [empty] mbox
1.77 0.00 3.91 0.44 84% 12% Waiting to get mbox
1.59 0.00 1.95 0.60 81% 18% Waiting to put mbox
5.37 3.91 9.77 0.91 65% 31% Delete mbox
16.66 13.67 27.34 1.42 90% 3% Put/Get mbox
2.62 1.95 5.86 0.92 68% 68% Init semaphore
3.84 1.95 7.81 0.47 81% 12% Post [0] semaphore
4.21 3.91 7.81 0.53 87% 87% Wait [1] semaphore
3.48 1.95 5.86 0.76 71% 25% Trywait [0] semaphore
3.60 1.95 5.86 0.62 78% 18% Trywait [1] semaphore
2.26 1.95 5.86 0.53 87% 87% Peek semaphore
1.89 0.00 1.95 0.12 96% 3% Destroy semaphore
16.05 13.67 29.30 1.40 59% 18% Post/Wait semaphore
2.38 1.95 3.91 0.67 78% 78% Create counter
2.01 0.00 3.91 0.35 84% 6% Get counter value
1.89 0.00 3.91 0.24 90% 6% Set counter value
4.58 3.91 5.86 0.88 65% 65% Tick counter
1.71 0.00 1.95 0.43 87% 12% Delete counter
3.84 1.95 7.81 0.36 87% 9% Create alarm
7.99 5.86 15.63 0.47 93% 3% Initialize alarm
2.01 0.00 3.91 0.35 84% 6% Disable alarm
6.53 5.86 13.67 1.01 75% 75% Enable alarm
2.32 1.95 3.91 0.59 81% 81% Delete alarm
4.76 3.91 7.81 1.01 59% 59% Tick counter [1 alarm]
19.53 17.58 23.44 0.24 90% 6% Tick counter [many alarms]
7.57 5.86 13.67 0.75 75% 21% Tick & fire counter [1 alarm]
98.57 97.66 105.47 1.14 96% 62% Tick & fire counters [>1 together]
22.15 21.48 27.34 0.96 71% 71% Tick & fire counters [>1 separately]
359.18 357.42 384.77 1.10 65% 31% Alarm latency [0 threads]
362.63 357.42 396.48 2.55 43% 27% Alarm latency [2 threads]
408.22 402.34 416.02 2.73 55% 21% Alarm latency [many threads]
378.63 375.00 494.14 2.56 93% 71% Alarm -> thread resume latency
9.78 5.86 19.53 0.00 Clock/interrupt latency
12.21 5.86 31.25 0.00 Clock DSR latency
12 0 316 (main stack: 752) Thread stack used (1120 total)
All done, main stack : stack used 752 size 2400
All done : Interrupt stack used 288 size 4096
All done : Idlethread stack used 276 size 2048
Timing complete - 30550 ms total
PASS:<Basic timing OK>
EXIT:<done>
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