erjinzhiyunsuan.v

基于simulink的二进制运算

//  -------------------------------------------------------------
// 
//  Module: erjinzhiyunsuan
//  Simulink Path: erjinzhiyunsuan
//  Created: 2009-02-17 14:11:51
//  Hierarchy Level: 0
// 
// 
//  -------------------------------------------------------------

`timescale 1 ns / 1 ns

module erjinzhiyunsuan
          (
           clk,
           reset,
           clk_enable
          );


  input   clk;
  input   reset;
  input   clk_enable;


  wire enb;
  real data3_out1;  // double
  real data1_out1;  // double
  wire [63:0] s;  // ufix64
  real data4_out1;  // double
  real data2_out1;  // double
  wire [63:0] s_1;  // ufix64
  wire signed [31:0] th;  // int32
  wire signed [31:0] hu;  // int32
  wire signed [31:0] de;  // int32
  wire signed [31:0] g;  // int32
  wire signed [15:0] Add4_out1;  // int16
  wire signed [15:0] sum_1;  // int16
  wire signed [15:0] add_cast;  // int16
  wire signed [15:0] add_cast_1;  // int16
  wire signed [16:0] add_temp;  // sfix17
  wire signed [15:0] sum_2;  // int16
  wire signed [15:0] add_cast_2;  // int16
  wire signed [15:0] add_cast_3;  // int16
  wire signed [16:0] add_temp_1;  // sfix17
  wire signed [15:0] add_cast_4;  // int16
  wire signed [15:0] add_cast_5;  // int16
  wire signed [16:0] add_temp_2;  // sfix17

  assign enb = clk_enable;
  initial
    begin
      data3_out1 = 1.0011001000000000E+007;
    end

  always @* data1_out1 <= data3_out1;


  assign s = $realtobits(data1_out1);
  initial
    begin
      data4_out1 = 1.0011001000000000E+007;
    end

  always @* data2_out1 <= data4_out1;


  assign s_1 = $realtobits(data2_out1);
  Subsystem   u_Subsystem   (.clk(clk),
                             .reset(reset),
                             .enb(enb),
                             .In1(s),  // ufix64
                             .In2(s_1),  // ufix64
                             .Out1(th),  // int32
                             .Out2(hu),  // int32
                             .Out3(de),  // int32
                             .Out4(g)  // int32
                             );
  assign add_cast = th[15:0];
  assign add_cast_1 = hu[15:0];
  assign add_temp = add_cast + add_cast_1;
  assign sum_1 = add_temp[15:0];

  assign add_cast_2 = sum_1;
  assign add_cast_3 = de[15:0];
  assign add_temp_1 = add_cast_2 + add_cast_3;
  assign sum_2 = add_temp_1[15:0];

  assign add_cast_4 = sum_2;
  assign add_cast_5 = g[15:0];
  assign add_temp_2 = add_cast_4 + add_cast_5;
  assign Add4_out1 = add_temp_2[15:0];


endmodule  // erjinzhiyunsuan