tset.v

dds编程代码 希望对别人有帮助 其功能是根据dds的原理编写

`timescale  1ns/1ns
module  test();
    reg  clk;
    reg  [1:0]wavemode;
    reg  [23:0]phaseadder;
    reg  [23:0]data; 
    wire  [8:0]qwave;
    dds f0(clk,wavemode,data,qwave);
  initial
   begin   clk=1'b0;
           wavemode=2'b10;
           data=24'h001024;
           phaseadder=24'h000000;
    end
   always   
         begin  #50  clk=~clk;  end
endmodule