boxing.v

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//综合输出模块：zonghe.v
`timescale  1ns/1ns
  module  boxing(clk,address,wavemode,qwave);
     input  clk;
     input  [1:0]wavemode;
     input  [9:0]address;
     output [8:0]qwave;
     reg    [8:0]qwave;
     wire   [8:0]qwave1,qwave2,qwave3;
     fangbo s1(clk,address,qwave1);
     sanjiaobo s2(clk,address,qwave2);
     sinbo s3(clk,address,qwave3);
        always@(posedge  clk)
          case(wavemode)
            2'b01:qwave=qwave1;
            2'b10:qwave=qwave2;
            2'b11:qwave=qwave3;
          endcase
  endmodule