dds.v

来自「dds编程代码 希望对别人有帮助 其功能是根据dds的原理编写」· Verilog 代码 · 共 17 行

//信号发生器顶层模块：dds.v
`timescale  1ns/1ns
  module dds(clk,wavemode,data,qwave);
     input clk;
     input [1:0]wavemode;
     input [23:0]data; 
     output [8:0]qwave;
     wire [1:0]wavemode;
     wire [23:0]data;
     wire [9:0]address;
     wire [8:0]qwave;
        counter f1(clk,data,address); //累加锁存
        boxing f2(clk,address,wavemode,qwave);//波形产生及输出
  endmodule