spi.v

三线spi接口

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:56:51 03/19/2009 
// Design Name: 
// Module Name:    spi 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
/***********************************************/
//SPI控制器，串行发送数据，更新CMOS内部寄存器
/***********************************************/
module spi( clk,
				rst_n,
				address_in,
				data_in,
				spi_clk,
				spi_in,
				spi_enable,
				finish_flag
				);
	input clk;							//模块主时钟;
	input rst_n;						//模块复位信号;
	input [3:0] address_in;			//接收待发送的地址;
	input [11:0] data_in;			//接收待发送的数据;
	output spi_clk,spi_in,spi_enable;	//SPI串行信号输出;
	reg spi_clk,spi_in,spi_enable;
	output finish_flag;				//传递完毕标志位;
	reg finish_flag;
	
	reg [3:0] address_buf;			//缓存接收到的地址信息;
	reg [11:0] data_buf;				//缓存接收到的数据信息;
	reg [6:0] counter32;				//计数器产生spienable使能信号;
//	reg [2:0] counter3;				//计数器产生串行位流更新使能信号;
	reg clk_div2;						//提供分频信号;
	
//主时钟二分频,作为spiclk的信号源	
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				clk_div2 <= 1'b0;
			else
				clk_div2 <= ~clk_div2;				
		end
//通过计数器产生spienable信号
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				counter16 <= 5'h00;
			else if(counter32 <34)
						counter32 <= counter32 + 5'h1;
					else
						counter32 <= 5'h00;
		end

	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				spi_enable <= 1'b0;
			else if(counter32 >=32)
						spi_enable <= 1'b1;
					else
						spi_enable <= 1'b0;
		end
//generate spiclk signal;
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				spi_clk <= 1'b0;
			else if(!spi_enable)
						spi_clk <= ~spi_clk;
					else
						spi_clk <= 1'b0;
		end

//串行发送数据
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				spi_in <= 1'bz;
			else if(spi_enable)
						spi_in <= 1'bz;
					else
						case(counter32)
						0: spi_in <= address_buf[3];
						2: spi_in <= address_buf[2];
						4: spi_in <= address_buf[1];
						6: spi_in <= address_buf[0];
						8: spi_in <= data_buf[11];
					  10: spi_in <= data_buf[10];
					  12: spi_in <= data_buf[9];
					  14: spi_in <= data_buf[8];
					  16: spi_in <= data_buf[7];
					  18: spi_in <= data_buf[6];
					  20: spi_in <= data_buf[5];
					  22: spi_in <= data_buf[4];
					  24: spi_in <= data_buf[3];
					  26: spi_in <= data_buf[2];
					  28: spi_in <= data_buf[1];
					  30: spi_in <= data_buf[0];
						endcase
		end
//传递完成使能信号
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				finish_flag <= 1'b0;
			else if(counter32 >=32)
						finish_flag <= 1'b1;
					else
						finish_flag <= 1'b0;				
		end
//接收待发送的数据
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				begin
					address_buf <= 4'h00;
					data_buf <= 12'h00;
				end
			else if(spi_enable)
						begin
							address_buf <= address_in;
							data_buf <= data_in;
						end
					else
						begin
							address_buf <= 4'h00;
							data_buf <= 12'h00;
						end
						
		end


endmodule