front.stx

来自「FPGA设计中乒乓设计的源代码」· STX 代码 · 共 25 行

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "front.v"
Module <front> compiled
No errors in compilation
Analysis of file <"front.prj"> succeeded.
 
CPU : 0.03 / 0.42 s | Elapsed : 0.00 / 0.00 s
 
--> 

Total memory usage is 77136 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)