test.fdo

FPGA设计中乒乓设计的源代码

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Dec 26 22:44:39 涓?鍥芥爣鍑嗘椂闂? 2007
##
vlib work
vlog  clk_contrl.v
vlog  front.v
vlog  a_task.v
vlog  b_task.v
vlog  back.v
vlog  pingpang.v
vlog  test.tfw
vlog  "D:/LijunYang_software/xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work test glbl
do {test.udo}
view wave
add wave *
view structure
view signals
run -all