transcript

FPGA设计中乒乓设计的源代码

# Reading d:/lijunyang_software/modelsim5.7/tcl/vsim/pref.tcl 
# do test.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module clk_contrl
# 
# Top level modules:
# 	clk_contrl
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module front
# 
# Top level modules:
# 	front
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module a_task
# 
# Top level modules:
# 	a_task
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module b_task
# 
# Top level modules:
# 	b_task
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module back
# 
# Top level modules:
# 	back
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module pingpang
# 
# Top level modules:
# 	pingpang
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module test
# 
# Top level modules:
# 	test
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test glbl 
# Loading work.test
# Loading work.pingpang
# Loading work.clk_contrl
# Loading work.front
# Loading work.a_task
# Loading work.b_task
# Loading work.back
# Loading work.glbl
# .wave
# .structure
# .signals
# No errors or warnings.
# Break at test.tfw line 61
# Simulation Breakpoint: Break at test.tfw line 61
# MACRO ./test.fdo PAUSED at line 19
restart
run
run -all
# No errors or warnings.
# Break at test.tfw line 61
quit